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<== Date ==> <== Thread ==>

Subject: Re: Dev lib off-board register access
From: Andrew Johnson <anj@aps.anl.gov>
To: "Rees, NP (Nick)" <nick.rees@diamond.ac.uk>
Cc: EPICS tech-talk <tech-talk@aps.anl.gov>
Date: Fri, 14 Jul 2006 12:08:19 -0500
Rees, NP (Nick) wrote:

One of our problems is that on one of the boards the interrupt acknowledge register is write only - so a read from it generates a bus error, which isn't as pretty as it should be. I presume (from Andrews email) that if we read a value from any other readable VME memory location, that will flush the pipeline just as well. Is that correct?

Yup, that's what the book says and my experience has confirmed that. You might want to check that all your VMEbus master windows are marked as Guarded in the sysPhysMemDesc[] table too, since that's the mechanism by which the CPU is told it can't reorder read and write I/O operations within this memory range.


- Andrew
--
Not everything that can be counted counts,
and not everything that counts can be counted.
  -- Albert Einstein

References:
RE: Dev lib off-board register access Rees, NP (Nick)

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