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Subject: | Re: Dev lib off-board register access |
From: | Eric Bjorklund <[email protected]> |
To: | EPICS tech-talk <[email protected]> |
Date: | Thu, 13 Jul 2006 10:26:29 -0600 |
Hi Nick,
at least on MV2300 and MV5100, caching is disabled for VME access anyway. You should only need to care about cache if using DMA.
Flushing the processor and bus pipelines is something different as far as I understand the problem. Calling cacheFlush probably just gives the system some time process the write and calling printf instead might have the same effect. The BSP (see sysLib.c and sysALib.s) often uses the assembler instructions eieio and sync after register access.
Maybe using the BSP functions sysOutByte() and friends is the only correct way to access external registers? But I don't know if those functions are implemented on all board architectures or what they are called on other operating systems.
Rees, NP (Nick) wrote:
So I suggest, as a minimum:
devGetBigEndianRegisters( volatile void * from, void * to, size_t nobj,
size_t size );
devSetBigEndianRegisters( void * from, volatile void * to, size_t nobj,
size_t size );
devGetLittleEndianRegisters( volatile void * from, void * to, size_t
nobj, size_t size );
devSetLittleEndianRegisters( void * from, volatile void * to, size_t
nobj, size_t size );
Peter Denison gave me the following link to the Linux kernel sources
which gives a reasonable description of sync, lwsync, eieio and wmb, rmb
etc.
http://lxr.linux.no/source/include/asm-ppc64/system.h#L18
I assume that at the bottom of cacheFlush and cacheInvalidate is a sync
instruction on the PPC, but I might be wrong. I certainly don't see it.
The problem we have found with the 5500 is, I think, related to the
problem outlined in the 2002 tech-talk thread. The processor MMU may
know the VME memory isn't cached, but there is also a cache in the VME
chip (why, I don't know) and that has to be forced as well.