Experimental Physics and
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at least on MV2300 and MV5100, caching is disabled for VME access anyway. You should only need to care about cache if using DMA. Flushing the processor and bus pipelines is something different as far as I understand the problem. Calling cacheFlush probably just gives the system some time process the write and calling printf instead might have the same effect. The BSP (see sysLib.c and sysALib.s) often uses the assembler instructions eieio and sync after register access. Maybe using the BSP functions sysOutByte() and friends is the only correct way to access external registers? But I don't know if those functions are implemented on all board architectures or what they are called on other operating systems. Unfortunately I am not familiar enough with the PPC architecture to know what eieio and sync really do and what instructions to use on other processors. Dirk Rees, NP (Nick) wrote: This is really a follow-up to the 2002 thread on PowerPC caching:
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ANJ, 02 Sep 2010 |
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