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<== Date ==> <== Thread ==>

Subject: Re: Dev lib off-board register access
From: Kate Feng <feng1@bnl.gov>
To: Eric Bjorklund <bjorklund@lanl.gov>
Cc: EPICS tech-talk <tech-talk@aps.anl.gov>
Date: Fri, 14 Jul 2006 09:45:58 -0400
Eric Bjorklund wrote:

> .
>
> In my experience I have usually been able to always get non-DMA drivers to work by always declaring the register pointer as "volatile" (which is more to defeat compiler optimization and not really a caching issue) and following the last write with a dummy read to the same register (to flush the pipeline).

Do you mean the dummy read following the last write is needed for
only vxWorks-mvme5500 ? Or  is it  needed for almost all the powrPC
boards using  VxWorks ? Does it apply to all the VME boards ?

Is this implemented in other vxWorks-PPC  site such as APS or any other
facility ?  I did'nt notice this in synApp which was written by APS, but I am
off-site now that I can'nt verify the code.

>
>
> DMA devices are another story. For these it would be nice to have devLib routines to do cache invalidation and flushing. Byte order is another issue. For non-DMA devices, however, I don't think caching is a problem.

At NSLS, we use RTEMS-MVME5500 BSP that I developed, which
enables the hardware cache snoop on CPU local memory  for all the
DMA applications so that the sofware caching  is not  needed  yet.
However, the VME  space is marked as Non-Cacheable and
Guarded in the BSP.

Regards,
Kate


Replies:
Re: Dev lib off-board register access Andrew Johnson
Re: Dev lib off-board register access Eric Bjorklund
RE: Dev lib off-board register access Rees, NP (Nick)
References:
Dev lib off-board register access Rees, NP (Nick)
Re: Dev lib off-board register access Dirk Zimoch
Re: Dev lib off-board register access Eric Bjorklund

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