Experimental Physics and
Industrial Control System

<[email protected]> · Tue, 27 Sep 2016 07:59:03 +0000

Hi Tim,

From: Mooney, Tim M. [mailto:[email protected]]
> But I do have one question already.  For registers added to the FPGA, all one
> needs is the physical address and a call to mmap(), and those registers are
> available to user-space code. Is this because memory added to the FPGA is
> unknown to the cache?

I'm a little bit vague about the details, but in essence this is right.  I think the kernel is configured to set up all of memory as cacheable and the remaining address space as uncacheable.  On our system /proc/iomem shows address space 00000000-3fffffff as System RAM and the rest as various bits of IO space.  Actually, I think this information is probably in the device tree, come to think of it.

>  If so, it there a way to tell the cache not to look at a
> section of the processor's physical memory, so the same strategy might also
> work there?

There probably is, and it's probably not a great idea!  You could in principle tell the kernel to reserver a dedicated block of memory for IO on booting, or you could probably mark memory as uncacheable in chunks after allocating it with __get_free_pages(), but it certainly wouldn't be easier than the recipe I've suggested!  Also, reading from uncached memory is liable to be *very* slow.

I think that it's normally better to cooperate with the cache rather than bypassing it, and I suspect you'd need to dig deeper into the kernel than I ever have to do this right.  I can give you some sample code for an unrelated Zynq project if it would help you, but you'd need to completely rewrite it for your application, of course.

On the device tree, it is mostly a closed book to me, but I see this entry in mine:

	memory { device_type = "memory"; reg = <0x0 0x40000000>; };

This is consistent with the iomem entry.

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Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System