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<== Date ==> <== Thread ==>
Subject: Re: Implementation of an EPICS IOC on an Embedded Soft Core ProcessorUsing Field Programmable Gate Arrays
From: David Kline <[email protected]>
To: [email protected]
Cc: tech-talk <[email protected]>
Date: Mon, 18 May 2009 13:12:02 -0500
sorry to sound like a commercial ... 8--]

basically, i derived my work from eric norum in the controls group and steve ross in
the detector pool. also, i had spoken with someone @ jlab a few years ago regarding
the work doug curry had done.

the ucdimm is running rtems (4.7.1) and i used eric's 'bridge' in quartus-ii as the
communication mechanism between the ucdimm and the fpga.

- the bc-071 has a vme foot print and connectors for an application-specific daughter
board (next to p2) and another set of connectors (next to p1) which marry to the ucdimm
carrier board developed by the aps controls group. i think these are viewable from the link
i sent previously. it can reside on vme under vxworks control, or using the ucdimm as a
standalone unit or boot its application from the network.

- the ucdimm carrier board can be replaced with a transition board that allows it to be installed
in a vme crate, thus providing access to the cyclone-ii from vme. the daughter boards employs
the remaining fpga io for application specific functionality. i've developed a 'generic digital io'
(derived from steve ross) daughter board that is used in one sector as a 32ch scaler and in
another sector as a flexible timing module with 20ns resolution for ccd shutter control. a board
is being developed with ecl inputs / outputs for counting the number of photons given a particular
bunch over a number of accelerator cycles. another board is in development to provide lvds inputs
and outputs as well as a camera link interface for controlling a camera in a sector performing fuel
spray experiments.

in addition, i've developed a daughter board which provides a pc104 interface (8bit). this was
developed to retain the investment we made in pc104 hardware, such as the 8ch smart a/d from
sensoray, or the 4ch dac ruby module from the diamond system's corporation. in the past, i used
the pc104-based fpga module from tri-m systems (http://www.tri-m.com/products/engineering/fpga104kit.html)
but it proved to be more costly than the ucdimm / fpga combo (cannot beat ~$100 for the ucdimm  8--] ).

finally, my opinion, it's free ... i'm completely sold on the idea of having the ucdimm as a cheap epics
interface and using the fpga for real-time data acquisition and control for certain applications. also, i
use the ebrick module (2-2-2) in synapps as a departure point for ucdimm-based applications. generally,
this will work out of the box. to date only prototype work has been accomplished on vme.

hth,
/david

Silver wrote: 
hi, David:

  A good picture of advertisement. :) Is it embedded EPICS on vxWorks/FPGA? or additional CPU board are needed?

======= At 2009-05-18, 23:33:26 you wrote: =======

  
in bcda, we had a similar conclusion and decided to go with a ucdimm  / 
altera cyclone-ii fpga pair
(http://www.aps.anl.gov/bcda/hardware/custom_hw/projects/bc071/BC071_VME_uCDIMM_IO.jpg).

/david

Matt Bickley wrote:
    
Silver wrote:
      
hi, all:

  I have read an article titled as "Implementation of an EPICS IOC on 
an Embedded Soft Core Processor Using Field Programmable Gate Arrays" 
of 10th ICALEPCS. It's written by Douglas Curry of Jefferson Lab. In 
the end of this paper, it's said "We have also cross-compiled EPICS 
for ?Clinux and are presently in the beginning stages of executing 
and troubleshooting embedded IOCs on the Nios II architecture."
  Is this work finished? I am very interested in it. Would anybody 
kindly tell me more details? thanks a lot in advance.
        
Doug Curry did not get much further along in this work at
Jefferson Lab.  He was very successful, and it looked
to have a lot of promise.  For reasons of standardization
and long-term stability, we decided to pursue an alternative
path...namely, using PC104 embedded processors running RTEMS
to provide a control system interface to FPGA-based systems.
Since that time Doug has moved on to SNS.

      
-- 

+-------------------------------------------------+
David M. Kline                   [email protected]
Beamline Controls and Data Acquisition (BCDA)
Argonne National Laboratory, Advanced Photon Source
Argonne IL, 60439                      630.252.8639
 ---------------------------------------------
         Beamlines R Us -- EBRICKs Rule
+-------------------------------------------------+ 

    
= = = = = = = = = = = = = = = = = = = =
			

Best regards				 
Geyang 2009-05-19



  


-- 

+-------------------------------------------------+
David M. Kline                   [email protected]
Beamline Controls and Data Acquisition (BCDA)
Argonne National Laboratory, Advanced Photon Source
Argonne IL, 60439                      630.252.8639
  ---------------------------------------------
          Beamlines R Us -- EBRICKs Rule
+-------------------------------------------------+
References:
Implementation of an EPICS IOC on an Embedded Soft Core Processor Using Field Programmable Gate Arrays Silver
Re: Implementation of an EPICS IOC on an Embedded Soft Core Processor Using Field Programmable Gate Arrays Matt Bickley
Re: Implementation of an EPICS IOC on an Embedded Soft Core Processor Using Field Programmable Gate Arrays David Kline
Re: Re: Implementation of an EPICS IOC on an Embedded Soft Core ProcessorUsing Field Programmable Gate Arrays Silver
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