Subject: |
Re: Implementation of an EPICS IOC on an Embedded Soft Core Processor Using Field Programmable Gate Arrays |
From: |
David Kline <[email protected]> |
To: |
Matt Bickley <[email protected]> |
Cc: |
tech-talk <[email protected]> |
Date: |
Mon, 18 May 2009 10:33:24 -0500 |
in bcda, we had a similar conclusion and decided to go with a ucdimm /
altera cyclone-ii fpga pair
(http://www.aps.anl.gov/bcda/hardware/custom_hw/projects/bc071/BC071_VME_uCDIMM_IO.jpg).
/david
Matt Bickley wrote:
Silver wrote:
hi, all:
I have read an article titled as "Implementation of an EPICS IOC on
an Embedded Soft Core Processor Using Field Programmable Gate Arrays"
of 10th ICALEPCS. It's written by Douglas Curry of Jefferson Lab. In
the end of this paper, it's said "We have also cross-compiled EPICS
for ?Clinux and are presently in the beginning stages of executing
and troubleshooting embedded IOCs on the Nios II architecture."
Is this work finished? I am very interested in it. Would anybody
kindly tell me more details? thanks a lot in advance.
Doug Curry did not get much further along in this work at
Jefferson Lab. He was very successful, and it looked
to have a lot of promise. For reasons of standardization
and long-term stability, we decided to pursue an alternative
path...namely, using PC104 embedded processors running RTEMS
to provide a control system interface to FPGA-based systems.
Since that time Doug has moved on to SNS.
--
+-------------------------------------------------+
David M. Kline [email protected]
Beamline Controls and Data Acquisition (BCDA)
Argonne National Laboratory, Advanced Photon Source
Argonne IL, 60439 630.252.8639
---------------------------------------------
Beamlines R Us -- EBRICKs Rule
+-------------------------------------------------+
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