Experimental Physics and
Industrial Control System

Kate Feng <[email protected]> · Fri, 08 Sep 2006 13:36:21 -0400

Till Straumann wrote:

Finally, IMHO it is not *that* big of an issue. If we use an interrupt

to signal bus-errors, as you point out, it might be delivered
asynchronously

[as it would anyways as soon as posted transactions are involved]

and therefore harder to debug but you still get a notification that
something

is wrong.

Yes, it is not a big issue to use an interrupt to signal bus-errors.
The concern for the Tsi148 is that:
If the transaction was a VMEbus read,
the VME Master completes the Linkage Module command by
filling the buffer with a data pattern of all ones.

It is even possible [for coupled transactions] to suspend the
faulty thread and halt the system if it happens in an ISR.
Can you verify what you meant  "possible"?  Does it happen
automatically without extra coding for sure ?  Do you
mean "nested interrupt" ?  Since nested interrupt is hard
to implement as what Andrew pointed out.  If the bus error
happened in an ISR for a VME read, the read data is not
valid any more, which could, if not checked,  lead to unwanted
VME writes on valid addresses by the following code in the ISR
because the write buffer is flushed only for posted writes that is up
to where the bus error is.
Regards,
Kate

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System