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<== Date ==> <== Thread ==>

Subject: Re: VME Bus Error handling on MVME3100 and MVME6100 boards
From: Kate Feng <[email protected]>
To: Andrew Johnson <[email protected]>, [email protected]
Date: Fri, 08 Sep 2006 08:49:00 -0400
Andrew Johnson wrote about mvme6100:

> The only sure-fire way around this problem is to check
> the Tempe chip's VMEbus Exception Attributes Register after every
> write operation and every read that returns an all-1s bit pattern

Just a clarification:
Should'nt most applications be terminated upon bus error ?
For those applications, it seems that the overhead for the
VME read/write is necessary to be considered only inside
the related ISRs or in the related non-ISR routines where
the interrupt has to be disabled, which is rare.

FYI, the following is the hardware timing sequence on bus error :

MV6436x PCI master termination :

If there is no target response to the initiated transaction
within four clock cycles (five clocks in case of DAC transaction),
the master issues a Master Abort event.  The master de-asserts
FRAME# and on the next cycle de-asserts IRDY#. Also, the Interrupt
Cause register's MMAbort bit is set and an interrupt is generated,
if not masked.

The master supports three types of target termination:
. Retry
. Disconnect
. Target Abort

If a target terminates a transaction with Disconnect, the Mv6436x master
re-issues the transaction from the point it was disconnected.

If a target terminates a transaction with Retry, the Mv6436x master
re-issues the transaction.

Andrew Johnson wrote about the Tsi148:

>The Tsi148 PCI Target never terminates a transaction with a
>Target-abort and SIGTA (Signalled Target Abort): The Tsi148 does not
>generate a target abort, therefore this bit is hard-wired to a logic 0.

In its user manual:
"Ihe target can terminate a transaction with a retry or a
disconnect. ......."

>When the VME Master encounters one of these conditions, any write data
>in the buffers is removed (flushed). If the transaction was a VMEbus read,
>the VME Master completes the Linkage Module command by
>filling the buffer with a data pattern of all ones.

"One of the conditions"  is "when a VME bus transfer initiated
by the VME master does not complete successfully".

Kate


Replies:
Re: VME Bus Error handling on MVME3100 and MVME6100 boards Andrew Johnson
References:
Re: VME Bus Error handling on MVME3100 and MVME6100 boards Kate Feng
Re: VME Bus Error handling on MVME3100 and MVME6100 boards Andrew Johnson
Re: VME Bus Error handling on MVME3100 and MVME6100 boards Kate Feng

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