Dear Friends,
I reported a problem using GPIB driver with Force CPU-40 as IOC some time ago.
Recently I finaly pointed out the cause of problem and find the solution.
When you wants to access shared memory of CPU40 cpu board from VMEbus side in
A24 mode, you need to set up some registers on CPU40 properly. BSP we have
assumes you don't use A24 mode to access shared memory and does not set up
register. And also sysLocalToBusAdrs returns ERROR when it is called with
VME_AM_STD_xxx as address space specifier.
Another source of trouble is the lack of sysA24Malloc/sysA24Free funtions
in VxWorks/BSP for CPU40 we use. GP-IB driver uses ordinary malloc/free
funtions in place of sysA24Malloc/sysA24Free functions. It causes "cache
incoherence" problem when GP-IB board uses DMA.
I enclosed set of routines to fix these at the end of e-mail.
Thnak you,
Noboru Yamamoto
KEKB Accelerator Control Group.
KEK, JAPAN
=================== code starts here =========================================
#include <cacheLib.h>
#include <sysLib.h>
#include <vme.h>
/* The following two lines are copied from vw/config/frc40/config.h> */
#define LOCAL_MEM_LOCAL_ADRS 0x00000000
#define LOCAL_MEM_BUS_ADRS (0x01000000*(sysProcNumGet()+1))
/* 16M*proc# */
typedef unsigned char uchar;
void enableSlaveA24(void ){
/* this routine is based on the code from Dr. Furukawa of KEK */
uchar * p;
uchar u;
p = (uchar *)0xff800c00; /* pointer to PI/T1 */
*(p+0x03) = 0xff; /* PB all output, PBDDR */
*(p+0x09) = 0x01; /* defaulted to 0x1000000 in VxWorks PBDR */
*(p+0x09) = ((unsigned int) LOCAL_MEM_BUS_ADRS)>>24;
/* A31-A24 of Local_MEM_BUS address is PDDR data*/
p = (uchar *)0xff800e00; /* pointer to PI/T2 *
*(p+0x04) = 0xa8; /* PC7 output, PCDDR */
*(p+0x0c) &=0x7f; /* enable A24 slave, PCDR */
/* PC7=0 means A32/A24 mode */
}
/*******************************************************************************
*
* sysLocalToBusAdrs - convert a local address to a bus address
*
* This routine gets the VMEbus address that accesses a specified local memory
* address.
*
* RETURNS: OK, or ERROR if the mapping is not possible.
*
* SEE ALSO: sysBusToLocalAdrs()
*/
STATUS sysLocalToBusAdrs
(
int adrsSpace, /* bus address space in which busAdrs resides */
char *localAdrs, /* local address to convert */
char **pBusAdrs /* where to return bus address */
)
{
if ((int) localAdrs < LOCAL_MEM_LOCAL_ADRS || localAdrs >= sysMemTop ())
{
/* this is off-board memory - just return local address */
*pBusAdrs = localAdrs;
return (OK);
}
/*
* this is on-board memory - map to bus address space;
* the following memory mapping is established in sysProcNumSet():
* - only processor 0 has memory on bus,
* - the memory is placed in EXT space at
* address LOCAL_MEM_BUS_ADRS.
*/
switch (adrsSpace)
{
case VME_AM_SUP_SHORT_IO:
case VME_AM_USR_SHORT_IO:
return (ERROR); /* no A16 access to RAM */
case VME_AM_STD_SUP_PGM:
case VME_AM_STD_SUP_DATA:
case VME_AM_STD_USR_PGM:
case VME_AM_STD_USR_DATA:
if( localAdrs > (char *) 0xffffff) {
logMsg(" sysLocalToBus conversion error: %8.8x\n",localAdrs);
return (ERROR);
}
else {
*pBusAdrs =localAdrs + LOCAL_MEM_BUS_ADRS ;
return (OK); /* slave A24 access enabled */
}
case VME_AM_EXT_SUP_PGM:
case VME_AM_EXT_SUP_DATA:
case VME_AM_EXT_USR_PGM:
case VME_AM_EXT_USR_DATA:
*pBusAdrs = localAdrs + LOCAL_MEM_BUS_ADRS;
return (OK);
default:
return (ERROR);
}
}
/* Froce CPU40 BSP lacks sysA24Malloc/sysA24Free. */
/* However it causes some problem if you woulid like to */
/* enable Slave A24 mode access to shared memory. */
/* These routines below avoid cache coherence problem */
/* in such a sisuation. */
/* Written by N. Yamamoto, KEK for EPICS tool kit. */
extern int devLibA24Debug ; /* Debugging flag */
void *sysA24Malloc(size_t size)
{
if (devLibA24Debug){
logMsg("sysA24Malloc(%p) entered\n", (unsigned long)size,0,0,0,0,0);
}
return ((void *) cacheDmaMalloc(size));
}
void sysA24Free(void * pBlock)
{
if (devLibA24Debug){
logMsg("sysA24Free(%p) entered\n", (unsigned long)pBlock,0,0,0,0,0);
}
cacheDmaFree(pBlock);
}
=================== code ends here =========================================
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