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<== Date ==> <== Thread ==>

Subject: RE: asyn or caput rate limits?
From: "Brown, Garth" <gwbrown@slac.stanford.edu>
To: Mark Rivers <rivers@cars.uchicago.edu>, "'tech-talk@aps.anl.gov'" <tech-talk@aps.anl.gov>
Cc: "Gang Huang \(ghuang@lbl.gov\)" <ghuang@lbl.gov>, "Carlos Serrano \(cserrano@lbl.gov\)" <cserrano@lbl.gov>, "Vamsi Vytla \(VKVytla@lbl.gov\)" <VKVytla@lbl.gov>, "Ratti, Alessandro G" <ratti@slac.stanford.edu>, "Larry Doolittle \(ldoolitt@recycle.lbl.gov\)" <ldoolitt@recycle.lbl.gov>
Date: Sat, 29 Apr 2017 22:30:48 +0000
Thanks, Mark. I think your first suggestions are better suited to this situation, and it seems to clear up the problem. Their code sometimes writes the tag register, writes something else, writes the tag register again, and still saw the problem.  I had included the asyn:READBCK=1 early in development, thinking it would be useful. I had been updating it with a value read from the FPGA and setting the error status if it didn't match the value written. But I don't think the users are even looking at the readback value.
It now passes my tight loop test.

Garth

-----Original Message-----
From: Mark Rivers [mailto:rivers@cars.uchicago.edu] 
Sent: Saturday, April 29, 2017 3:23 PM
To: Brown, Garth; 'tech-talk@aps.anl.gov'
Cc: Gang Huang (ghuang@lbl.gov); Carlos Serrano (cserrano@lbl.gov); Vamsi Vytla (VKVytla@lbl.gov); Ratti, Alessandro G; Larry Doolittle (ldoolitt@recycle.lbl.gov)
Subject: RE: asyn or caput rate limits?

Hi Garth,

One potential solution to this would be to use a waveform record to hold the list of values to be written in rapid succession.  Then you can add waveform record support to your driver. This will ensure that your driver gets all of the values.  

If your driver sets the value to the SHELL_0_DSP_TAG_W parameter in the parameter library for each element of the array and does callbacks, then the ao record value will update with each value in the array because you are using the info tag asyn:READBCK=1.

Mark

________________________________________
From: tech-talk-bounces@aps.anl.gov [tech-talk-bounces@aps.anl.gov] on behalf of Brown, Garth [gwbrown@slac.stanford.edu]
Sent: Saturday, April 29, 2017 4:54 PM
To: 'tech-talk@aps.anl.gov'
Cc: Gang Huang (ghuang@lbl.gov); Carlos Serrano (cserrano@lbl.gov); Vamsi Vytla (VKVytla@lbl.gov); Ratti,       Alessandro G; Larry Doolittle (ldoolitt@recycle.lbl.gov)
Subject: asyn or caput rate limits?

I'm working with a user who wants to write different values to the same PV in quick succession, as part of the asynPortDriver interface I'm writing to their FPGA. Sometime I'm seeing the right number of writes, but some values are duplicated while others are skipped. It's the sort of thing you might see if, while the record is processing from write #1, two more writes came in, the value of write #2 was replaced by the value from write #3 before the record processed a second and third time. Or if the write function were called before the value updated. Is there a known issue/workaround/fix?

Executive summary
When I write a sequence of numbers to the PV in a tight loop, these are the values my asynPortDriver sees:

2017/04/29 14:32:43.092 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 2
2017/04/29 14:32:43.096 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 2
2017/04/29 14:32:43.096 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 4
2017/04/29 14:32:43.100 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 4
2017/04/29 14:32:43.100 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 6
2017/04/29 14:32:43.101 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 7
....

Details:
I'm using base 3-14-12, asyn 4-26.

The record:
record(ao, "$(P)SHELL_0_DSP_TAG_W")
{
    field( PINI, "NO")
    field( DTYP, "asynInt32")
    field( OUT,  "@asyn($(PORT),0) SHELL_0_DSP_TAG_W")
    field( SCAN, "Passive")
    field( HOPR, "0x000000FF")
    field( LOPR, 0)
        field(PREC, 3)
    info( asyn:READBACK, "1")
}

My asynPortDriver subclass constructor:
scllrfAsynPortDriver::scllrfAsynPortDriver(const char *drvPortName, const char *netPortName, int maxAddr, int paramTableSize)
: asynPortDriver(drvPortName,
                maxAddr, /* maxAddr */
                paramTableSize,
                asynInt32Mask | asynFloat64Mask | asynInt8ArrayMask | asynOctetMask | asynDrvUserMask | asynFloat32ArrayMask | asynInt32ArrayMask | asynInt16ArrayMask | asynUInt32DigitalMask, /* Interface mask */
                asynInt32Mask | asynFloat64Mask | asynInt8ArrayMask | asynOctetMask | asynEnumMask | asynFloat32ArrayMask | asynInt32ArrayMask | asynInt16ArrayMask | asynUInt32DigitalMask,  /* Interrupt mask */
                ASYN_CANBLOCK | ASYN_MULTIDEVICE,
                1, /* Autoconnect */
                epicsThreadPriorityMedium,
                0), /* Default stack size*/
                _singleMsgQ (maxMsgSize, maxMsgSize), isShuttingDown_(0), netSendCount_(0), lastResponseCount_ (0), netWaitingRequests_(0),
                newWaveAvailable_(0), newWaveRead_ (0), p_RunStop (stop)
{
...

        status=pasynCommonSyncIO->connect(netPortName, 0, &pCommonAsynUser_, 0);
        status=pasynOctetSyncIO->connect( netPortName,0,&pOctetAsynUser_,0);

}
And  in a subclass of that,
    createParam(Shell0DspTagWString, asynParamInt32, &p_Shell0DspTagW);


My write function:
asynStatus scllrfAsynPortDriver::writeInt32(asynUser *pasynUser, epicsInt32 value)
{
        int function = pasynUser->reason;
        asynStatus status = asynSuccess;
    const char *paramName;
    FpgaReg regSendBuf[minRegPerMsg]; // LBNL reports problems when smaller requests are sent
    std::fill( regSendBuf, regSendBuf + sizeof( regSendBuf )/sizeof( *regSendBuf), (FpgaReg)  {flagReadMask,blankData} );
    int chan;

        epicsTimeStamp timeStamp; getTimeStamp(&timeStamp);

    // Some registers have more than 1 "channel"
    getAddress(pasynUser, &chan);

    /* Fetch the parameter string name for possible use in debugging */
    getParamName(function, &paramName);
    asynPrint(pasynUser, ASYN_TRACEIO_DRIVER, "--> %s: function=%d, %s channel %d, value %d\n",
                        __PRETTY_FUNCTION__, function, paramName, chan, value);

[snipped code that applies to other records]

        // Convert function to address & FpgaReg.
        status = functionToRegister(function, &regSendBuf[1]);
        if (status == asynSuccess) // Yes, this function is a register write
        {
                asynPrint(pasynUser, ASYN_TRACEIO_DRIVER,
                "%s: found function=%d, name=%s, at chan %d + %d\n",
                          __PRETTY_FUNCTION__, function, paramName, regSendBuf[1].addr, chan);
                regSendBuf[1].data = (int32_t) value;
                regSendBuf[1].addr += (uint32_t) chan; // Add offset for multi-element short arrays/channels
                htonFpgaRegArray(regSendBuf, sizeof( regSendBuf )/sizeof( *regSendBuf));
                // Add this write to the queue, to be sent in FIFO order
                _singleMsgQ.send(&regSendBuf[1], sizeof( FpgaReg ));
        }
[snipped more code that's only for other records]
    }

    /* Set the parameter in the parameter library. */
    status = (asynStatus) setIntegerParam(chan, function, value);
        /* Do callbacks so higher layers see any changes */
        status = (asynStatus) callParamCallbacks(chan, chan);

    if (status)
        epicsSnprintf(pasynUser->errorMessage, pasynUser->errorMessageSize,
                  "%s: status=%d, function=%d, name=%s, value=%d",
                                  __PRETTY_FUNCTION__, status, function, paramName, value);
    else
        asynPrint(pasynUser, ASYN_TRACEIO_DRIVER,
              "<-- %s: function=%d, name=%s, channel=%d, value=%d\n",
                          __PRETTY_FUNCTION__, function, paramName, chan, value);
    return status;
}
And in its subclass, a writeInt32 that handles other records, but for this one just calls the base class:
asynStatus scllrfPRCextra::writeInt32(asynUser *pasynUser, epicsInt32 value)
{
        int function = pasynUser->reason;
        asynStatus status = asynSuccess;
    const char *paramName;

    /* Fetch the parameter string name for possible use in debugging */
    getParamName(function, &paramName);
    asynPrint(pasynUser, ASYN_TRACEIO_DRIVER, "--> %s: function=%d, %s, set to %d\n",
                        __PRETTY_FUNCTION__, function, paramName, value);

    if (function == [stuff related to other records])

    scllrfAsynPortDriver::writeInt32(pasynUser, value);

    if (status)
        epicsSnprintf(pasynUser->errorMessage, pasynUser->errorMessageSize,
                  "%s: status=%d, function=%d, name=%s, value=%d",
                                  __PRETTY_FUNCTION__, status, function, paramName, value);
    else
        asynPrint(pasynUser, ASYN_TRACEIO_DRIVER,
              "<-- %s: function=%d, name=%s, value=%d\n",
                          __PRETTY_FUNCTION__, function, paramName, value);
    return status;
}

My test python script, which is admittedly more stress than the real user code:
>>> for tag in range(2, 130):
...     print tag
...     epics.caput('RFS2:B15:SHELL_0_DSP_TAG_W', tag)

I run this with full logging enabled, wireshark running, and camonitor the PV.
Wireshark also shows skipped values, but it's hard to cut and paste.
The camonitor output:
$ camonitor RFS2:B15:SHELL_0_DSP_TAG_W
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:24:44.576161 129
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.095349 2
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.099380 4
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.100659 6
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.103658 7
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.108133 9
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.112623 11
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.117054 13
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.121404 15
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.125565 17
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.129752 19
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.134049 21
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.138429 23
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.142946 25
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.147262 27
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.151441 29
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.155728 31
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.159995 33
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.164318 35
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.168588 37
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.172850 39
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.177182 41
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.181530 43
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.185834 45
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.190245 47
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.194498 49
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.198795 51
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.203126 53
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.207354 55
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.211672 57
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.215988 59
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.220357 61
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.224644 63
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.228970 65
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.236086 67
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.239083 69
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.243416 71
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.247694 73
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.252008 75
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.256299 77
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.260561 79
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.264789 81
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.269028 83
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.273272 85
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.277554 87
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.282715 89
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.293223 91
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.296529 93
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.301078 95
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.308187 97
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.314345 99
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.320082 101
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.323234 103
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.327370 104
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.333308 106
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.336291 108
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.340847 110
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.345322 112
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.349998 114
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.354558 116
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.359349 118
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.367851 120
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.374274 122
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.380801 124
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.383976 126
RFS2:B15:SHELL_0_DSP_TAG_W     2017-04-29 14:32:43.388351 128

Extracted from the console log:
 2017/04/29 14:24:44.572 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 129
2017/04/29 14:32:43.092 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 2
2017/04/29 14:32:43.096 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 2
2017/04/29 14:32:43.096 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 4
2017/04/29 14:32:43.100 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 4
2017/04/29 14:32:43.100 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 6
2017/04/29 14:32:43.101 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 7
2017/04/29 14:32:43.104 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 7
2017/04/29 14:32:43.104 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 9
2017/04/29 14:32:43.109 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 9
2017/04/29 14:32:43.109 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 11
2017/04/29 14:32:43.113 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 11
2017/04/29 14:32:43.113 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 13
2017/04/29 14:32:43.117 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 13
2017/04/29 14:32:43.118 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 15
2017/04/29 14:32:43.122 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 15
2017/04/29 14:32:43.122 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 17
2017/04/29 14:32:43.126 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 17
2017/04/29 14:32:43.126 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 19
2017/04/29 14:32:43.130 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 19
2017/04/29 14:32:43.130 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 21
2017/04/29 14:32:43.134 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 21
2017/04/29 14:32:43.134 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 23
2017/04/29 14:32:43.139 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 23
2017/04/29 14:32:43.139 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 25
2017/04/29 14:32:43.143 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 25
2017/04/29 14:32:43.143 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 27
2017/04/29 14:32:43.147 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 27
2017/04/29 14:32:43.147 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 29
2017/04/29 14:32:43.152 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 29
2017/04/29 14:32:43.152 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 31
2017/04/29 14:32:43.156 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 31
2017/04/29 14:32:43.156 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 33
2017/04/29 14:32:43.160 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 33
2017/04/29 14:32:43.160 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 35
2017/04/29 14:32:43.164 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 35
2017/04/29 14:32:43.165 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 37
2017/04/29 14:32:43.169 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 37
2017/04/29 14:32:43.169 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 39
2017/04/29 14:32:43.173 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 39
2017/04/29 14:32:43.173 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 41
2017/04/29 14:32:43.177 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 41
2017/04/29 14:32:43.178 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 43
2017/04/29 14:32:43.182 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 43
2017/04/29 14:32:43.182 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 45
2017/04/29 14:32:43.186 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 45
2017/04/29 14:32:43.186 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 47
2017/04/29 14:32:43.190 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 47
2017/04/29 14:32:43.191 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 49
2017/04/29 14:32:43.195 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 49
2017/04/29 14:32:43.195 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 51
2017/04/29 14:32:43.199 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 51
2017/04/29 14:32:43.199 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 53
2017/04/29 14:32:43.203 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 53
2017/04/29 14:32:43.203 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 55
2017/04/29 14:32:43.208 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 55
2017/04/29 14:32:43.208 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 57
2017/04/29 14:32:43.212 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 57
2017/04/29 14:32:43.212 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 59
2017/04/29 14:32:43.216 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 59
2017/04/29 14:32:43.216 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 61
2017/04/29 14:32:43.221 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 61
2017/04/29 14:32:43.221 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 63
2017/04/29 14:32:43.225 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 63
2017/04/29 14:32:43.225 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 65
2017/04/29 14:32:43.229 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 65
2017/04/29 14:32:43.232 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 67
2017/04/29 14:32:43.236 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 67
2017/04/29 14:32:43.236 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 69
2017/04/29 14:32:43.239 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 69
2017/04/29 14:32:43.239 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 71
2017/04/29 14:32:43.244 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 71
2017/04/29 14:32:43.244 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 73
2017/04/29 14:32:43.248 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 73
2017/04/29 14:32:43.248 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 75
2017/04/29 14:32:43.252 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 75
2017/04/29 14:32:43.252 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 77
2017/04/29 14:32:43.256 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 77
2017/04/29 14:32:43.257 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 79
2017/04/29 14:32:43.261 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 79
2017/04/29 14:32:43.261 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 81
2017/04/29 14:32:43.265 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 81
2017/04/29 14:32:43.265 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 83
2017/04/29 14:32:43.269 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 83
2017/04/29 14:32:43.269 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 85
2017/04/29 14:32:43.273 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 85
2017/04/29 14:32:43.274 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 87
2017/04/29 14:32:43.278 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 87
2017/04/29 14:32:43.278 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 89
2017/04/29 14:32:43.283 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 89
2017/04/29 14:32:43.287 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 91
2017/04/29 14:32:43.294 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 91
2017/04/29 14:32:43.294 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 93
2017/04/29 14:32:43.297 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 93
2017/04/29 14:32:43.297 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 95
2017/04/29 14:32:43.301 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 95
2017/04/29 14:32:43.304 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 97
2017/04/29 14:32:43.308 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 97
2017/04/29 14:32:43.310 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 99
2017/04/29 14:32:43.315 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 99
2017/04/29 14:32:43.316 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 101
2017/04/29 14:32:43.320 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 101
2017/04/29 14:32:43.322 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 103
2017/04/29 14:32:43.323 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 104
2017/04/29 14:32:43.328 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 104
2017/04/29 14:32:43.329 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 106
2017/04/29 14:32:43.334 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 106
2017/04/29 14:32:43.334 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 108
2017/04/29 14:32:43.337 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 108
2017/04/29 14:32:43.337 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 110
2017/04/29 14:32:43.341 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 110
2017/04/29 14:32:43.341 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 112
2017/04/29 14:32:43.346 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 112
2017/04/29 14:32:43.346 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 114
2017/04/29 14:32:43.350 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 114
2017/04/29 14:32:43.350 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 116
2017/04/29 14:32:43.355 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 116
2017/04/29 14:32:43.355 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 118
2017/04/29 14:32:43.360 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 118
2017/04/29 14:32:43.364 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 120
2017/04/29 14:32:43.368 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 120
2017/04/29 14:32:43.370 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 122
2017/04/29 14:32:43.375 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 122
2017/04/29 14:32:43.377 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 124
2017/04/29 14:32:43.381 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 124
2017/04/29 14:32:43.381 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 126
2017/04/29 14:32:43.384 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 126
2017/04/29 14:32:43.384 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 128
2017/04/29 14:32:43.389 --> virtual asynStatus scllrfAsynPortDriver::writeInt32(asynUser*, epicsInt32): function=351, SHELL_0_DSP_TAG_W channel 0, value 128

Replies:
RE: asyn or caput rate limits? Mark Rivers
References:
asyn or caput rate limits? Brown, Garth
RE: asyn or caput rate limits? Mark Rivers

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