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<== Date ==> <== Thread ==>

Subject: RE: Asyn and devices with changing register map
From: "Mooney, Tim M." <mooney@aps.anl.gov>
To: "Rivers, Mark L." <rivers@cars.uchicago.edu>, "'Konrad, Martin'" <konrad@frib.msu.edu>, EPICS Tech Talk <tech-talk@aps.anl.gov>
Date: Mon, 9 Jan 2017 18:09:56 +0000
This is how softGlueZynq handles FPGA addresses.  A record connected to a register location looks like this:

record(longout,"$(P)$(H)$(SIG)") {
	field(PINI, "YES")
	field(DTYP,"asynUInt32Digital")
	field(OUT,"@asynMask($(PORT),$(ADDR),0xffffffff)REG32")
}

ADDR is the integer offset from a base address in the FPGA.  The driver (drvZynq.c, in this case) infers the FPGA component name from the from the asyn port name, and gets the FPGA base address mapped into user space from that name.

Tim Mooney (mooney@aps.anl.gov) (630)252-5417
Beamline Controls Group (www.aps.anl.gov)
Advanced Photon Source, Argonne National Lab


________________________________________
From: tech-talk-bounces@aps.anl.gov [tech-talk-bounces@aps.anl.gov] on behalf of Mark Rivers [rivers@cars.uchicago.edu]
Sent: Friday, January 06, 2017 4:58 PM
To: 'Konrad, Martin'; EPICS Tech Talk
Subject: RE: Asyn and devices with changing register map

One way to do this would be to use the asyn "addr" parameter

In this implementation you might only have a few parameters:

INT8_REGISTER
INT16_REGISTER
INT32_REGISTER
FLOAT32_REGISTER
FLOAT64_REGISTER

The $(ADDR) macro in the link can specify the register address as in the following example records.

# Register address 6, int8
record(longout, "$(P)$(R)Gain")
{
   field(DTYP, "asynInt32")
   field(OUT,  "@asyn($(PORT),6,$(TIMEOUT))INT8_REGISTER")
}

# Register address 10, int32
record(longout, "$(P)$(R)Offset")
{
   field(DTYP, "asynInt32")
   field(OUT,  "@asyn($(PORT),10,$(TIMEOUT))INT32_REGISTER")
}

# Register address 22, float64
record(longout, "$(P)$(R)Frequency")
{
   field(DTYP, "asynFloat64")
   field(OUT,  "@asyn($(PORT),22,$(TIMEOUT))FLOAT64_REGISTER")
}

You would set the flag ASYN_MULTIDEVICE and specify the maximum register address in the call to the asynPortDriver constructor.

It's not super-efficient in terms of memory, because you will have 5 parameters for each address, and only 1 being used.  But we are probably only talking a few kilobytes at most.

Mark

-----Original Message-----
From: Konrad, Martin [mailto:konrad@frib.msu.edu]
Sent: Friday, January 06, 2017 4:31 PM
To: EPICS Tech Talk; Mark Rivers
Subject: Asyn and devices with changing register map

Hi Mark,
I am intending to implement a driver for an FPGA-based device based on
asynPortDriver. I am wondering how to deal with devices which are under
heavy development resulting in frequent changes to their register map.
In this context I am looking for a simple and clean way to tie records
to a certain address.

In a world without Asyn I would implement a driver that simply reads the
address and the type of a register from the INP/OUT fields of my
records. This could be changed easily (even by an FPGA engineer) without
recompiling the driver and all configuration data is in the record
definition. Note that I'm fine with this slightly harder to read data in
the INP/OUT field. Usually the record's name, the description field, and
if necessary additional comments provide sufficient information about
what the address stands for.

Using Asyn it seems like I need to populate Asyn's paramList which in
the case of most drivers seems to be a hard-coded mapping between names
and addresses. Are there any drivers that populate this dynamically on
IOC start from a configuration file or even from the EPICS database file?

Thanks a lot,

Martin

--
Martin Konrad
Control System Engineer
Facility for Rare Isotope Beams
Michigan State University
640 South Shaw Lane
East Lansing, MI 48824-1321, USA
Tel. 517-908-7253
Email: konrad@frib.msu.edu



References:
Asyn and devices with changing register map Konrad, Martin
RE: Asyn and devices with changing register map Mark Rivers

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