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<== Date ==> <== Thread ==>
Subject: Re: Newport XPS-Q8 and Motor Record - armv5teb architecture
From: Stephen Beckwith <[email protected]>
To: "J. Lewis Muir" <[email protected]>
Cc: Tonia Batten <[email protected]>, "[email protected]" <[email protected]>
Date: Mon, 5 May 2014 23:00:24 -0400
Intel is Little Endian - ARM can be either - how is the ARMv5 setup?  Big Endian or Little Endian?
What OS are you dealing with?  What compiler?
What happens if you move the double and int?  Could be padding issue in how the compilers for different ISA handle the alignment.  Is the Intel a 64bit CPU? (I know ARMv5 is not, that’s a “StrongArm” variant basically or Marvell. . .
Does the ARM compiler being used has proper library support for double?
Stephen Beckwith



On Sat, May 3, 2014 at 8:39 PM, J. Lewis Muir <[email protected]> wrote:
On 5/3/14, 5:32 PM, Mark Rivers wrote:
> Any idea how this could happen?

Hi, Mark.

Compiler bug?  Maybe try turning off all optimizations?

Lewis

Replies:
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Tonia Batten
References:
RE: Newport XPS-Q8 and Motor Record - armv5teb architecture Mark Rivers
Re: Newport XPS-Q8 and Motor Record - armv5teb architecture J. Lewis Muir
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