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<== Date ==> <== Thread ==>

Subject: Re: CSR/CR questions
From: "Bjorklund, Eric A" <bjorklund@lanl.gov>
To: EPICS tech-talk <tech-talk@aps.anl.gov>
Cc: Bai Jiaoni <baijn@ihep.ac.cn>
Date: Mon, 29 Oct 2012 23:46:35 +0000
Oops.  Make that:

if (slotBase)
    CSRSetBase(slotBase, 7, 0x40000, VME_AM_STD_SUP_DATA);

(no "not" in the test -- I should never try to program in an e-mail :-}

On Oct 29, 2012, at 5:33 PM, Bjorklund, Eric A wrote:


On Oct 29, 2012, at 1:55 AM, Bai Jiaoni wrote:
Dear Professor,
I want to use Geogrephic addressing to set the base address. I have some questions about CR/CSR address space. If I have the hardware in the 6 VME slot. I konw the CSR/CR space of this slot is 6<<19. CSR/CR includes two parts: CR and CSR. CR addressing space is from 0x0000 to 0x00FFF, which is about configuration information. The CSR space is from 0x7FC00 to 0x7FFFF. The table 10-13 of attachment is the CSR space. and the table 10-8 is one of the ADER.

1 Why one CSR/CR has 8 ADER instead of only one?

The 8 ADER's (along with the 8 DAWPER's, 8 AMCAP's, 8 XAMCAP's and 8 ADEM's) allow a VME card to have multiple address spaces.  For example, a waveform generator card may have a small area in A16 space for control and status registers, and a larger area in A32 space for storing the waveform.  I've never seen a card that needed all 8 address spaces, but at least they are ready if somebody builds one!

2 How does each ADER decoder? If the solt is 6, how to set the base address?

On one level, this is a hard question to answer because I don't completely understand your WriteToVme8 routine.  I assume that VCSR is the cpu address of the start of CR/CSR space.  Shifting nGeo (which I assume is the slot number?) back and forth by 4 bits puzzles me.  However, assuming that is what you intended to do, I think I do see one problem.  Your second call to WriteToVme8 writes nGeo>>4 (which would be 0 if nGeo is 6) to 7ffdf -- which is the byte where the address mode should be written on ADER 7.  The byte addresses for ADER 7 (if I've done the addition correctly) should be:
  7ffd3: High order byte of the VME base address
  7ffd7: 2nd highest order byte of the VME base address
  7ffdb: 3rd highest order byte of the VME base address
  7ffdf: VME Address mode (shifted left 2 bits)

On another level, however, the question is much easier.  Since you are using EPICS, just call the CSRSetBase routine from the devlib2 library.
If you don't have the devlib2 library already, you can get it at:

The following code can be used to set the base address (in ADER 7) of the module in slot 6 to 0x40000 in A24 space:

/* Make sure Slot 6 has a CR/CSR enabled card in it (if so, returns base CR/CSR address for slot 6) */
volatile unsigned char* slotBase = devCSRProbeSlot(6);

/* Set the base address to 0x40000 (A24) */
if (!slotBase)
    CSRSetBase(slotBase, 7, 0x40000, VME_AM_STD_SUP_DATA);

Hope this is helpful.

-Eric Bj.

The below information is our hardware base address setting information:

void addr()
{

 printf(">>VME:: Basic Global Address Configure.\n");
 quickctrl_addr=0xfc0270;/* quick control address */
 quickctrl_toff=0x18;       /*sign of turning off quick control*/
 csr1_haddr=0x700! 43;     /*cblt csr1 high 8 bits offset address*/
 ader3_addr=0x7ffdc;     /*address decoder compre registers address*/
 CLKader3_haddr=0x7ffdf+0x3;
 CLKader2_haddr=0x7ffdb+0x3;
 CLKader1_haddr=0x7ffd7+0x3;
 CLKader0_haddr=0x7ffd3+0x3;

 HPset_regaddr=0x10400;  /*HPTDC setup reg*/
 ader2_haddr=0x7ffd8+0x3;/*address decoder compre register2 high 8 bits address */
 ader3_haddr=0x7ffdc+0x3;/*address decoder compre register3 high 8 bits address */
 /*HighThresh,LowThresh,Constvoltage,SelfTestSignAmp,QTLowThresh,QTHighThresh;*/
 LTReg_addr=0x40000,HTReg_addr=0x40004,QTCurr_addr=0x40008,SLEFTest_addr=0x4000c,QTHTrig_addr=0x40010,QTLTrig_addr=0x40014;
 EventReg_addr=0xc;
 Quickctrl_offaddr=0x7ffb;
 /*L1_num;*/
  LUT_addr=0x30000;
 
 printf("VME:: Constant Address Set.\n");
}

 

WriteToV! me8((nGeo<<19)+ader2_haddr, VCSR, nGeo<<4));

WriteToVme8((nGeo<<19)+ader3_haddr, VCSR, nGeo>>4));

--

Jiaoni Bai 
Institute of High Energy Physics, CAS
NO.19 of Yuquan Road, Shijingshan District, Beijing, China

 


 
<CSR.png>



References:
CSR/CR questions Bai Jiaoni
Re: CSR/CR questions Bjorklund, Eric A

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