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<== Date ==> <== Thread ==>

Subject: RE: EPICS channel access performance test
From: "Hill, Jeff" <johill@lanl.gov>
To: tanushyam bhattacharjee <gettanu@yahoo.co.in>, "tech-talk@aps.anl.gov" <tech-talk@aps.anl.gov>
Date: Thu, 12 Jul 2012 17:17:49 +0000

Hi,

 

Ø  However, when we are performing the same for ARM9 and

Ø  FPGA-microblaze the final slope is not coming with the data

Ø  generated though the ioc CPU is overloaded and it maintains

Ø  the plateau for ever.

Ø   

Ø  Can anybody explain the reason?

 

One important difference with an embedded processor might be that, if a hardware floating point unit isn’t available or in the case of the soft-core instantiated, then one can expect that record processing can be limited by the performance of software floating point emulation; in contrast the ca server code and the network driver don’t tend to use as much floating point as compared to the record processing. Since every ca put to a process passive field can trigger record processing then this could be a limiting factor. In that situation you might observe that you find the limit of the CPU before you find the limit imposed by the maximum throughput in the network interface.

 

Jeff

 

From: tech-talk-bounces@aps.anl.gov [mailto:tech-talk-bounces@aps.anl.gov] On Behalf Of tanushyam bhattacharjee
Sent: Monday, July 09, 2012 10:11 AM
To: tech-talk@aps.anl.gov
Subject: EPICS channel access performance test

 

We want to measure channel access performance say for an integer data type using "catime" tool and as per our expectation we have got the result in a linux-x86 platform which concludes something like this:

(i) The plot "No. of PV" vs "Average Time" is like a bath tub curve.
(ii) The initial slope explains the network overhead is more than the size of PV
(iii) The middle plateau explains the optimised performance of CA as the number of PVs are high.
(iv) The final slope explains that CPU is overloaded with no of PVs and from here we can draw the threshold optimised performance of CA for an ioc.


However, when we are performing the same for ARM9 and FPGA-microblaze the final slope is not coming with the data generated though the ioc CPU is overloaded and it maintains the plateau for ever.

Can anybody explain the reason?


Tanushyam Bhattacharjee, Shantanoo Sahoo

Variable Energy Cyclotron Centre
Kolkata,India

 


References:
EPICS channel access performance test tanushyam bhattacharjee

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