EPICS Controls Argonne National Laboratory

Experimental Physics and
Industrial Control System

1994  1995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  <20122013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024  Index 1994  1995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  <20122013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024 
<== Date ==> <== Thread ==>

Subject: RE: EPICS channel access performance test
From: "Hill, Jeff" <[email protected]>
To: tanushyam bhattacharjee <[email protected]>, "[email protected]" <[email protected]>
Date: Thu, 12 Jul 2012 17:17:49 +0000

Hi,

 

Ø  However, when we are performing the same for ARM9 and

Ø  FPGA-microblaze the final slope is not coming with the data

Ø  generated though the ioc CPU is overloaded and it maintains

Ø  the plateau for ever.

Ø   

Ø  Can anybody explain the reason?

 

One important difference with an embedded processor might be that, if a hardware floating point unit isn’t available or in the case of the soft-core instantiated, then one can expect that record processing can be limited by the performance of software floating point emulation; in contrast the ca server code and the network driver don’t tend to use as much floating point as compared to the record processing. Since every ca put to a process passive field can trigger record processing then this could be a limiting factor. In that situation you might observe that you find the limit of the CPU before you find the limit imposed by the maximum throughput in the network interface.

 

Jeff

 

From: [email protected] [mailto:[email protected]] On Behalf Of tanushyam bhattacharjee
Sent: Monday, July 09, 2012 10:11 AM
To: [email protected]
Subject: EPICS channel access performance test

 

We want to measure channel access performance say for an integer data type using "catime" tool and as per our expectation we have got the result in a linux-x86 platform which concludes something like this:

(i) The plot "No. of PV" vs "Average Time" is like a bath tub curve.
(ii) The initial slope explains the network overhead is more than the size of PV
(iii) The middle plateau explains the optimised performance of CA as the number of PVs are high.
(iv) The final slope explains that CPU is overloaded with no of PVs and from here we can draw the threshold optimised performance of CA for an ioc.


However, when we are performing the same for ARM9 and FPGA-microblaze the final slope is not coming with the data generated though the ioc CPU is overloaded and it maintains the plateau for ever.

Can anybody explain the reason?


Tanushyam Bhattacharjee, Shantanoo Sahoo

Variable Energy Cyclotron Centre
Kolkata,India

 


References:
EPICS channel access performance test tanushyam bhattacharjee

Navigate by Date:
Prev: Re: EDM Segmentation fault John William Sinclair
Next: Re: Re: EDM Segmentation fault Zhang Yuliang
Index: 1994  1995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  <20122013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024 
Navigate by Thread:
Prev: EPICS channel access performance test tanushyam bhattacharjee
Next: New version of LabVIEW-EPICS-interface CA Lab Carsten Winkler
Index: 1994  1995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  2008  2009  2010  2011  <20122013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024 
ANJ, 18 Nov 2013 Valid HTML 4.01! · Home · News · About · Base · Modules · Extensions · Distributions · Download ·
· Search · EPICS V4 · IRMIS · Talk · Bugs · Documents · Links · Licensing ·