Experimental Physics and
Industrial Control System

Andrew Johnson <[email protected]> · Tue, 22 Nov 2011 10:27:28 -0600

Hi Zen,

On 2011-11-21 Szalata, Zenon M. wrote:
> Now, I load the IOC software, without errors.  However, when I enable
> interrupts in the SIS module, for each trigger (gate) I get the following
> error:
> 
> interrupt:
> Clearing VMEbus exception, attrib reg TEMPE_VEAT = 0xc00ccd00

TEMPE_VEAT is the Tsi148 chip's VMEbus Exception Attributes Register, which 
stores information about bus errors.  You can get the Tsi148 PCI/X-to-VME Bus 
Bridge User Manual from Tundra to find the full register definition, but that 
particular value means the following:

0x80000000 = VES: Register contains exception data
0x40000000 = VEOF: More exceptions happened after this one
0x00080000 = BERR: It was a bus error
0x00040000 = LWORD* asserted
0x00000000 = not WRITE, so it was a read cycle
0x00000000 = not IACK, so it was a regular I/O operation
0x00008000 = DS1* asserted
0x00004000 = DS0* asserted
0x00000d00 = AM=0x0d, A32 Supervisory data access

There is another register TEMPE_VEAL which would give you the A32 address 
where the bus error occurred if you read it.

So basically your code is trying to read a D32 value from an A32 location with 
a supervisory AM, but it's not getting any response (or the target is 
rejecting an access of that AM or size).

This could have a number of causes, and solving it might need you to change 
the configuration of the SIS board, or the BSP's settings of the VME master 
windows.

HTH,

- Andrew
-- 
Optimization is the process of taking something that works and
replacing it with something that almost works, but costs less.
-- Roger Needham

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System