Experimental Physics and
Industrial Control System

For LANSCE LLRF they need the real-estate provided by 6u boards, and for DAQ
the bandwidth between the FPGA and the analog modules isn't appearing to be
sufficient in cRIO. So for those systems we need either cPCI, VME, or uTCA.
If we have a centralized CPU then the bandwidth in cPCI Express, VME/VXS, or
uTCA for DAQ interconnects looks attractive. Another option which we are
looking at is to just run EPICS embedded on every one of the (Ethernet
directly connected) DAQ/LLRF modules thereby eliminating the system
interconnect as a bottleneck/complexity between the DAQ/FPGA hardware and
switched Ethernet.
----------what fpga are you using for this? We looked at putting a power PC core onto the FPGA, then we found out that this would not be supported on their next generation FPGA. We have been looking at running the micro blaze processor on it - and using a canned modbus server to talk to it over a 1Git Ethernet port.

Are you integrating timing in the compact Rio?
Why use the proprietary backplane in place of just dedicated fast serial interfaces?