EPICS Home EPICS Controls Argonne National Laboratory

Experimental Physics and
Industrial Control System

Format page
for printing


Search Tech-talk
1994  1995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  <2008>  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024  Index 1994  1995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  <2008>  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024 
<== Date ==> <== Thread ==>
Subject: RE: Gated ADC
From: "Kalantari Babak" <[email protected]>
To: "Leicester, PJ (Pete)" <[email protected]>
Cc: [email protected]
Date: Tue, 5 Aug 2008 12:49:06 +0200
Title: Message

Hi Pete,

 

I think 8401 Hytec IP module together with 8002 or 8004 (supports BLT as well) carrier is what you are looking for. Take a look at http://www.hytec-electronics.co.uk/8401UTM_ISS12.pdf

It has all the features you mentioned. I would use the INHIBIT input as the hardware gate. If the inhibit input is taken low the memory update is stopped and an interrupt is invoked (if enabled).

 

We have a driver for waveform but it may require very little modification only in the interrupt service routine to properly handle memory inhibit interrupts.

Let me know if you need the driver.

 

Regards,

Babak

 

 

 

From: [email protected] [mailto:[email protected]] On Behalf Of Leicester, PJ (Pete)
Sent: Dienstag, 5. August 2008 10:20
To: [email protected]
Subject: Gated ADC

 

1) Data collection controlled by a hardware gate signal such that data is collected into a buffer when the gate is enabled and when the gate is disabled an interrupt is generated so the data can be transferred into an I/O Intr processed waveform (or similar) record.

 

2) Sample rate up to at the least 10KHz but preferably 100KHz, and an absolute minimum of 16 bit.

 

3) Epics support for waveform record (or MCA or similar).

 

4) Preferably packaged as an IP module but a VME card would be OK.

 

Note that the essential feature is the gating of collection on the hardware signal. We do not want to trigger and collect a fixed number of samples (most ADC's do this).

 

Any suggestions would be gratefully received.

 

 

Replies:
RE: Gated ADC Mark Rivers
References:
Gated ADC Leicester, PJ (Pete)
Navigate by Date:
Prev: Gated ADC Leicester, PJ (Pete)
Next: RE: EPICS to Python / EPICS to Tcl Rowland, J (James)
Index: 1994  1995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  <2008>  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024 
Navigate by Thread:
Prev: Gated ADC Leicester, PJ (Pete)
Next: RE: Gated ADC Mark Rivers
Index: 1994  1995  1996  1997  1998  1999  2000  2001  2002  2003  2004  2005  2006  2007  <2008>  2009  2010  2011  2012  2013  2014  2015  2016  2017  2018  2019  2020  2021  2022  2023  2024 
ANJ, 02 Sep 2010 Valid HTML 4.01! · Home · News · About · Base · Modules · Extensions · Distributions · Download ·
· Search · EPICS V4 · IRMIS · Talk · Bugs · Documents · Links · Licensing ·