Experimental Physics and
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pastedGraphic.pdf This implies that external logic must assert TA within 2.5 ns (Time B0 minus time B1a) of the rising edge of CLKOUT. WIth the 64 MHz part this requirement was 5.625 ns, which wasn't easy to reach, but was possible. Do you do some tricky stuff like use the falling edge of CLKOUT to clock the section of the FPGA that drives the ColdFire TA* pin? -- Eric Norum <[email protected]> Advanced Photon Source Argonne National Laboratory (630) 252-4793
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ANJ, 02 Sep 2010 |
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