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<== Date ==> <== Thread ==>

Subject: Re: VME Bus Error handling on MVME3100 and 6100 boards
From: Andrew Johnson <[email protected]>
To: Till Straumann <[email protected]>
Cc: EPICS tech-talk <[email protected]>
Date: Wed, 23 Aug 2006 17:00:40 -0500
Till Straumann wrote:

I know about one device that will perform 97 bus accesses inside its ISR if it gets all-1s from its read cycles.

This driver should probably be rewritten. That many VME accesses from an ISR introduce serious latencies (even w/o bus timeouts).

Ah, but in normal operation it probably only performs 4 or 5 bus accesses at most; the problem comes if it thinks (from erroneous all-1s return values when reading its status registers) that it needs to do I/O on every one of its input and output channels. This could very easily happen if someone hot-swapped out a VME64 IPAC carrier board the device was mounted on (which shouldn't happen since this driver is not hot-swap safe, but it might still occur by mistake).


I agree that this is probably a bit of a straw man argument, but it illustrates the possible consequences of the Motorola + Tundra + Marvell design decisions on our existing software.

Anyone interested in MicroTCA to replace the now aging VMEbus?

- Andrew
--
There is considerable overlap between the intelligence
of the smartest bears and the dumbest tourists.
  -- Yosemite National Park Ranger

References:
VME Bus Error handling on MVME3100 and 6100 boards Andrew Johnson
Re: VME Bus Error handling on MVME3100 and 6100 boards Kate Feng
Re: VME Bus Error handling on MVME3100 and 6100 boards Till Straumann
Re: VME Bus Error handling on MVME3100 and 6100 boards Andrew Johnson
Re: VME Bus Error handling on MVME3100 and 6100 boards Andrew Johnson
Re: VME Bus Error handling on MVME3100 and 6100 boards Till Straumann
Re: VME Bus Error handling on MVME3100 and 6100 boards Andrew Johnson
Re: VME Bus Error handling on MVME3100 and 6100 boards Till Straumann

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