Experimental Physics and
Industrial Control System

Jukka Pietarinen <[email protected]> · Fri, 14 Jul 2006 19:23:27 +0300

Hi Eric,
Eric Bjorklund wrote:

On Jul 14, 2006, at 7:45 AM, Kate Feng wrote:

Do you mean the dummy read following the last write is needed for
only vxWorks-mvme5500 ? Or  is it  needed for almost all the powrPC
boards using  VxWorks ? Does it apply to all the VME boards ?

This is pretty much the case for any PPC using the Universe or Tempe VME
bridge. But my statement wasn't quite complete. As Andrew pointed out,
write posting ("pipeline") is mostly a problem with ISR's issuing a
write to clear the IRQ line and the write not actually happening until
after the ISR returns (as Andrew also pointed out, the dummy read does
not really have to be to the same register). So if your VME board
doesn't interrupt, you probably don't need to worry about it.

I believe it has to be the same register the write was targeted at. I
had problems accessing indirect RAM (sequence RAM of EVG) with MVME5500
running vxWorks. I first thought it was a compiler optimization problem
but the assembler listing was OK. I had to set up a VME bus analyzer to
see what was happening on the bus. My test code looks following:
STATUS ReadTest(MrfEvrStruct *pEvr, int ram)
{
  volatile MrfEvrStruct *pEr = pEvr;
  int address;
  int control;
  int data[4];
  /* Enable Ram for access */
  control = pEr->Control & ~(EVR_C_VMERS | EVR_C_RSTS | EVR_C_HRTBT |
                             EVR_C_IRQFL | EVR_C_LTS | EVR_C_NFRAM |
                             EVR_C_RSADR | EVR_C_RSFIFO | EVR_C_FF |
                             EVR_C_FNE | EVR_C_RSDLIRQ | EVR_C_RXVIO);
  if (ram == 2)
    control |= EVR_C_VMERS;
 pEr->Control = control;
  for (address = 0; address < 4; address++)
    {
      pEr->RamAddr = address;
      data[address] = pEr->RamData;
    }
}
In this code pEr->RamAddr and pEr->RamData are two consecutive two byte
words in VME A16 memory space and the contents of pEr->RamData depend on
the contents of pEr->RamAddr.
And this is what I see on the bus, which is really not what I wanted:
Read from pEr->Control
Read from pEr->RamData
Read from pEr->RamData
Write to pEr->Control
Read from pEr->RamData
Write to pEr->RamAddr
Read from pEr->RamData
Write to pEr->RamAddr
Write to pEr->RamAddr
Write to pEr->RamAddr
The only solution I found was to read back the address every time before
reading the data.
Regards,
Jukka

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System