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<== Date ==> <== Thread ==>

Subject: Re: Dev lib off-board register access
From: Eric Bjorklund <bjorklund@lanl.gov>
To: EPICS tech-talk <tech-talk@aps.anl.gov>
Date: Thu, 13 Jul 2006 10:26:29 -0600

On Jul 13, 2006, at 7:34 AM, Dirk Zimoch wrote:

Hi Nick,

at least on MV2300 and MV5100, caching is disabled for VME access anyway. You should only need to care about cache if using DMA.

Flushing the processor and bus pipelines is something different as far as I understand the problem. Calling cacheFlush probably just gives the system some time process the write and calling printf instead might have the same effect. The BSP (see sysLib.c and sysALib.s) often uses the assembler instructions eieio and sync after register access.

Maybe using the BSP functions sysOutByte() and friends is the only correct way to access external registers? But I don't know if those functions are implemented on all board architectures or what they are called on other operating systems.



In my experience I have usually been able to always get non-DMA drivers to work by always declaring the register pointer as "volatile" (which is more to defeat compiler optimization and not really a caching issue) and following the last write with a dummy read to the same register (to flush the pipeline).

DMA devices are another story. For these it would be nice to have devLib routines to do cache invalidation and flushing. Byte order is another issue. For non-DMA devices, however, I don't think caching is a problem.

Rees, NP (Nick) wrote:
So I suggest, as a minimum:
devGetBigEndianRegisters( volatile void * from, void * to, size_t nobj,
size_t size );
devSetBigEndianRegisters( void * from, volatile void * to, size_t nobj,
size_t size );
devGetLittleEndianRegisters( volatile void * from, void * to, size_t
nobj, size_t size );
devSetLittleEndianRegisters( void * from, volatile void * to, size_t
nobj, size_t size );

Another thing to consider is that some devices/registers require byte access, some may require word access, and some may require long access, so that should be added to your list.


On Jul 13, 2006, at 9:56 AM, Rees, NP ((Nick)) wrote:

Peter Denison gave me the following link to the Linux kernel sources
which gives a reasonable description of sync, lwsync, eieio and wmb, rmb
etc.

http://lxr.linux.no/source/include/asm-ppc64/system.h#L18

I assume that at the bottom of cacheFlush and cacheInvalidate is a sync
instruction on the PPC, but I might be wrong. I certainly don't see it.

The problem we have found with the 5500 is, I think, related to the
problem outlined in the 2002 tech-talk thread. The processor MMU may
know the VME memory isn't cached, but there is also a cache in the VME
chip (why, I don't know) and that has to be forced as well.

Actually, the problem in the 2002 tech-talk thread sounds more like the "Address Rot" problem Eric Norum described in: http://www.aps.anl.gov/epics/tech-talk/2003/msg00767.php -- which is more a problem of the board not meeting the VME spec. I've encountered this same problem with some of our custom boards
(see http://www.aps.anl.gov/epics/tech-talk/2004/msg00235.php )

-Eric Bj.



<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
Eric Björklund
Los Alamos Neutron Science Center (LANSCE)

phone: 505-667-6031 email: bjo@lanl.gov
<><><><><><><><><><><><><><><><><><><><><><><><><><><><>
Correspondence


Replies:
Re: Dev lib off-board register access Kate Feng
References:
Dev lib off-board register access Rees, NP (Nick)
Re: Dev lib off-board register access Dirk Zimoch

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