Title: Message
Dear All,
I have repeated the test with the present driver and our hardware, and the 'waitcount' is always 0.
If you are using an out of
date version of the driver you need to ensure that the configuration is as
follows....
Hy8402ipConfigure
( 1, 1, 1, 0,
0, 0, 12, 0)
# cardnumber =
1 # vmeslot = 1 #
Ipslot = 1
(0=A,1=B,2=C,3=D) #
intnum = 0 (Interrupt
Vector 0=find me one) #
doram = 1 (0 - Output via
Registers & ClockRate 12, 1 - Output via RAM & Set to passed ClockRate
) # clocksource = 0 (0 - internal, 1 - external) #
clockrate = 12 (10KHz) #
inhibit = 0 (no
inhibit)
Please
try this configuration with the clockrate set to 10Khz otherwise the register
will be updated at 1Hz, hence the large waitcount, and let me know if this
fixes.
Darrell Nineham
Hytec Electronics
Ltd.
Tel: +44 (0) 118 975
7770
Fax: +44 (0) 118 975
7566
Web: www.hytec-electronics.co.uk
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Coles,
Where does the DAC8402 reside in I/O
space? We had a similar problem with a serial driver in A32 space a few years
ago. As near as we could tell, the hardware was working fine, but the register
data seemed like it was being cached (even though it looked like the mapping
registers in the BSP were disabling caching for A32 space). Our fix was to
insert a cacheInvalidate (DATA_CACHE, (void *)statadr, 12); call into
the loop. We never really figured out whether this defeated the hardware
cache, or just broke the loop out of the CPU instruction pipeline, but it
worked.
You might try a bus-analyzer to see how many reads you really
are issuing to the DAC.
Hope this helps...
-Eric Bj.
On
Jun 16, 2005, at 10:47 AM, Sibley III, Coles wrote:
Hello, We
are using a Hytec DAC8402 at SNS for our beam loss monitor reference. The
driver uses far too much CPU time when we update 8 dacs every 5 seconds. In
fact it goes to 100% cpu usage. The offending code is below. We can fix the
code but the question is why does it take so long to set 16 register? The
8402 can be set to uses registers (for a typical dac application) or memory
(for arbitrary waveforms). We need the typical dac configuration, not the
arbitrary waveforms. We
are using a Motorola MVME5100 cpu. The
wait count goes to 600000 in our case, as if statadr was not declared as
volatile or the 512K of memory is getting loaded, not just the 16 registers.
Our WAITLIM has to be set to 1000000.
while(((*statadr&CSR_ARM) !=0) && waitcount <
WAITLIM)waitcount++;
if( waitcount < WAITLIM )
{
/* set dac value and rearm */
card->pMem->Data[signal]=val;
*statadr |=CSR_ARM;
} The
manual says: “ While
the unit is ARMed the DACs are constantly refreshed with the contents of the
registers which can be changed during this time. There is a delay which is
fixed of approximately 32us after ARM is set, before all the outputs change
together.” The
problem seems to be that the ARM stays high far longer than seems
reasonable, as the count rate indicates. The
initialization in st.cmd is: Hy8402Configure(1,1,0,0,0,0,0,0) Hy8402Configure(2,1,1,0,0,0,0,0) Any
suggestions? Coles
Sibley SNS
– ORNL Controls
Hardware Engineer 865-241-8055 [email protected]
<><><><><><><><><><><><><><><><><><><><><><><><><><><><> Eric
Björklund Los Alamos Neutron Science Center (LANSCE)
phone:
505-667-6031 email:
[email protected] <><><><><><><><><><><><><><><><><><><><><><><><><><><><> TSPA
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