Experimental Physics and
Industrial Control System

Kate Feng <[email protected]> · Fri, 26 Mar 2004 10:38:10 -0500

Hi Andrew,

Thank you very much for your patience and explaination.  Please
excuse me if  I miss something or misunderstand something
because  my  main focus  is on my own assignment.

Andrew Johnson wrote:

>  In the case of a Read cycle the Universe-2 will read the data
> off the VMEbus and pass it back to the CPU and finish the pending PCIbus
> read cycle.  However for a posted write cycle there is no reason to delay
> the CPU until the write completes, as it may be able to execute tens or
> even hundreds of instructions between performing the PCIbus write cycle
> and the VMEbus cycle completing.
>

I think you meant that the address pipelining on the UniverseII chip is
done via the posted write, which  makes more sense for me now.
However, I just did  a test and found out that one can disable the
posted write on the UniverseII running RTEMS-mvme5500.  With a
coupled cycle (posted write disable),  the VME bus master only
receives DTACK  when the data  transition is complete on the PCI bus.
This means that the VMEbus is unavailable to other masters while
the  PCI bus transaction is executed.

I agree with you  that one should enable the posted write by default.
However, it could be disabled, which means the address
pipelining on the  UniverseII could be disabled as well on the Mvme5500.
I thought the origianl issue is "to disable the  address pipelinig".
It  looks like you have a reason to disable the posted write
for the NI VME-MXI-1.   The trad off is to sacrifice the bandwidth
of the VME bus.  However, I do not know if  the decrease is
significant for your application.   I hope this helps.

Thanks,
Kate

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System