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<== Date ==> <== Thread ==>

Subject: Re: mvme5500 (was National Instruments VME-MXI-1 modules vs. modernVME CPU modules)
From: Kate Feng <[email protected]>
To: Andrew Johnson <[email protected]>
Cc: EPICS tech-talk <[email protected]>
Date: Tue, 23 Mar 2004 14:27:07 -0500
Hi Andrew,

Andrew Johnson wrote:

> Kate Feng wrote:
> >
> > Measured 60x bus bandwidth (MPC7450 + GT64260) :
> >     Pipelining  disabled : 177 MBytes/sec
> >     Pipelining  enabled :  589 MBytes/sec
> >
> > Thus, theoretically, one should be able to disable  the
> > address pipelining  of the mvme5500 (MPC7455 + GT64260).
>
> There's no way of getting 589MB/s through a regular VMEbus.
>

As what I said,  the data was published by Motorola.
The 60x bus is not a VME bus. The bandwidth between the two
is very different. However, they are related to each
other on the MVME5500. On the MVME5500, I jumper-selected
the 60x bus as the CPU bus interface.

>
> Address pipelining on the VMEbus (which was causing the problems with the
> VME-MXI-1 modules) is not related to address pipelining by the CPU on its
> local bus, which is .................

Do you have document to support the fact they are not related ?
I thought Tundra Universe-2 chip, who entertains the address
pipelining, is just a PCI-VME bridge, not a CPU. The address
pipelining you saw on the VME bus should originate from the CPU bus.
Otherwise, I imagine it would be a big SW/HW challenge to design a
working VME SBC if address pipelining of the VME is not related to
that of CPU.


I found your statement contradicted  with the last paragraph of the
http://www.vita.com/vmefaq/readwritecyc.html


> The
> VMEbus cycle timings are completely controlled by the Tundra Universe-2
> chip on Motorola PowerPC boards, and VMEbus address pipelining cannot be
> disabled.
>

Perhaps, the reason why you could not disable
the VMEbus address pipelining is because you were using the
MVME2100 and MVME5100, which do not have an intelligent system
controller between the CPU and the PCI-VME to disable the adress
pipeling. If you spared one minute to study the block diagram of
the MVME5500, you will understand it better.  The signals are
routed in the following order:

CPU <-> Marvell Discovery system controller (GT64260) <-> PCI <-> VME.

Thus, the addressing (especially the pipelining) should be
routed in such an order to be related to that of CPU.  If the system
controller disables the address pipelining before the address is
piped to the PCI bus, then the Tundra Universe-2 should not see
the address pipelining.


I ran a short test with the RTEMS BSP and confirmed that one can disable
the address pipelining on the MVME5500. However, I didn't (and do'nt
have to) conclude that the MVME5500 will solve the MXI-I problem.
It was just a clarification about the MVME5500..


Kate





Replies:
Re: mvme5500 (was National Instruments VME-MXI-1 modules vs. modernVME CPU modules) Andrew Johnson
References:
mvme5500 (was National Instruments VME-MXI-1 modules vs. modern VME CPU modules) Kate Feng
Re: mvme5500 (was National Instruments VME-MXI-1 modules vs. modern VME CPU modules) Andrew Johnson

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