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<== Date ==> <== Thread ==>

Subject: Re: National Instruments VME-MXI-1 modules vs. modern VME CPU modules
From: Till Straumann <[email protected]>
To: Eric Norum <[email protected]>
Cc: [email protected]
Date: Fri, 14 Nov 2003 18:16:18 -0800
Eric Norum wrote:
National Instruments VME-MXI-1 modules require that the VME A00-A31, AM0-AM5 and LWORD* bus lines remain stable until DS[AB]* have gone inactive. Unfortunately the VME specification has never guaranteed this.

As far as I remember, the spec even says that all slaves *must* work if the master does address pipelining.

The specification allows address pipelining (a.k.a. "address rot") to change the state of these lines as soon as DTACK* has been asserted.

Have you tried reducing the DTACK -> DS negation delay in the universe? (U2SPEC[READt27]) ?

Till


The APS has a rather large number of these modules. The flaw in the VME-MXI-1 has not caused problems because the modules have been used only with MVME167 CPU modules which do not perform address pipelining. We now want to upgrade some of these MVME167 IOCs to more modern CPU modules, but we've run into a problem. CPU modules with a UNIVERSE-II VME interface chip (all Motorola 2100, 5100 and 5500 series) do perform address pipelining which results in erratic data transfer from VME-MXI-1 modules. My guess is that it is likely that any modern CPU is going to cause the same problem.


We looked into fixing the problem by replacing some chips on the VME-MXI-1 but it appears that more than just minor surgery would be required.



References:
National Instruments VME-MXI-1 modules vs. modern VME CPU modules Eric Norum

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