Experimental Physics and
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Hi Eric, The problem analyzed and solved in the above paper is not the problem we are seeing. The DTACK* signal is clean on our bus and is appearing well after the VME-MXI-1 places data on the bus. The problem is that the VME-MXI-1 module does not latch the A00-A31 lines. This results in the following during a VME READ cycle: 1) CPU puts address information on bus and asserts AS* 2) CPU asserts DS0/1*. 3) VME-MXI-1 puts data on bus. 4) VME-MXI-1 asserts DTACK*. 5) CPU removes address information from bus and deasserts AS*. 6) VME-MXI-1 sees address lines change and puts scrambled data on bus. 7) CPU deasserts DS0/1* and latches in scrambled data........ Note that no amount of delaying the DTACK* signal from the VME-MXI-1 will help this situation (since this affects only the time between steps 3 and 4 above -- and the problem is occurring at steps 5/6). The only option is to replace all the address transceivers on the VME-MXI-1 with latching transceivers and all the address and address modifier receviers with latches. This is more board hacking than we want to get into. -- Eric Norum [email protected] Advanced Photon Source Phone: (630) 252-4793 Argonne National Laboratory
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ANJ, 10 Aug 2010 |
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