Experimental Physics and
Industrial Control System

Kazuro FURUKAWA <[email protected]> · Sat, 15 Nov 2003 07:10:21 +0900

Hi Eric, 

KEKB controls group analyzed the problem with PowerPC.  They described 
some details in 

<URL:http://www.slac.stanford.edu/econf/C011127/TUAP048.pdf>

>>> On Fri, 14 Nov 2003 10:52:45 JST,  Eric Norum <[email protected]> wrote;
> National Instruments VME-MXI-1 modules require that the VME A00-A31, AM0-AM5 and LWORD* bus lines remain stable until DS[AB]* have gone inactive.  Unfortunately the VME specification has never guaranteed this.  The specification allows address pipelini
> ng (a.k.a. "address rot") to change the state of these lines as soon as DTACK* has been asserted.
> 
> The APS has a rather large number of these modules.  The flaw in the VME-MXI-1 has not caused problems because the modules have been used only with MVME167 CPU modules which do not perform address pipelining.  We now want to upgrade some of these MVME1
> 67 IOCs to more modern CPU modules, but we've run into a problem.  CPU modules with a UNIVERSE-II VME interface chip (all Motorola 2100, 5100 and 5500 series) do perform address pipelining which results in erratic data transfer from VME-MXI-1 modules. 
>  My guess is that it is likely that any modern CPU is going to cause the same problem.
> 
> We looked into fixing the problem by replacing some chips on the VME-MXI-1 but it appears that more than just minor surgery would be required.

-----
Kazuro FURUKAWA <[email protected]>
 Linac,  High Energy Accelerator Research Organization (KEK), Japan

Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System