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<== Date ==> <== Thread ==>

Subject: RE: ISEG VHQ204L Driver (Really: PPC and VME)
From: "Luchini, Kristi" <luchini@SLAC.Stanford.EDU>
To: "'Andrew Johnson'" <anj@aps.anl.gov>, Kay-Uwe Kasemir <kasemir@lanl.gov>
Cc: "Burkhard W. Kolb" <b.kolb@gsi.de>, tech-talk@aps.anl.gov
Date: Thu, 25 Jul 2002 14:14:12 -0700
Hi, 

For this problem of forcing instructions to occur in the order that 
they appear in the code, I've used the asm instructions as well. To make
maintenance a bit easier I defined macros. Some but not all bsp's come with these
macros already. If not in a header file you may find it in some of the vxWorks source
for a bsp.

#define EIEIO       __asm__ volatile ("eieio")
#define EIEIO_SYNC  __asm__ volatile ("eieio;sync")
#define SYNC        __asm__ volatile ("sync")


Can you please send any fixes to the code back to me so that I can add these  changes.

 - Regards,
     Kristi

> -----Original Message-----
> From: Andrew Johnson [mailto:anj@aps.anl.gov]
> Sent: Thursday, July 25, 2002 9:14 AM
> To: Kay-Uwe Kasemir
> Cc: Burkhard W. Kolb; tech-talk@aps.anl.gov
> Subject: Re: ISEG VHQ204L Driver (Really: PPC and VME)
> 
> 
> Kay-Uwe Kasemir wrote:
> > 
> > Sounds like another way of forcing electrons out of the CPU
> > - if not even better than __asm__ volatile ("sync").
> 
> eieio is likely to be quicker - IIRC the sync causes the instruction
> pipeline to be stalled until the write is done as well, which isn't
> strictly necessary in this case (but useful when installing new CPU
> instructions).
> 
> > But what about the Universe II chip on most PPC boards
> > which has its own write pipeline?
> > Is there a "flush" register/command on it?
> 
> IIRC there's a bit somewhere that claims to show whether the write
> pipeline is empty, but when I tried putting code into the Universe
> interrupt handler to wait for this after running each ISR it made no
> difference to the "bad vme interrupt 0" error messages we 
> were getting. 
> The dummy read is the correct technique, as it also works on 
> the Motorola
> 68K boards that have a VMEchip2 if that's set to do write pipelining.
> 
> > (2) the fact that the memory regions mapped to VME are 
> configured as "not cacheable"
> >     in the vxWorks BSP's sysPhysMemDesc
> 
> BTW, I also mark our VME regions as Guarded, which supposedly 
> prevents the
> CPU from changing the order of writes to that address region.  I'm not
> sure if it makes any difference IRL, but it certainly makes me happier
> after having read about the possibility.
> 
> - Andrew
> -- 
> Larry McVoy: "Learn how to think in C++ but don't ever program in it."
> 

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