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<== Date ==> <== Thread ==>

Subject: Re: ISEG VHQ204L Driver
From: Andrew Johnson <anj@aps.anl.gov>
To: ahed aladwan <ahed.aladwan@psi.ch>
Cc: "Leng, Yongbin" <leng@bnl.gov>, tech-talk <tech-talk@aps.anl.gov>
Date: Wed, 24 Jul 2002 09:54:21 -0500
ahed aladwan wrote:
> 
> When the master (PPC MVME2304, vxWork 5.3.1) reads the data from the
> slave (A16, D16, address mod is 0x2D or 0x29), it seems that for some
> addresses the master get the data for the next address (+ 1 byte), using
> a logic analyzer to check the master read cycle (attached pdf file), I
> have noticed that because the master apply address pipelining
> (forcasting) and the slave dosen't latch the data (or address), I got
> wrong data.
> But what I can't understand why this happens only for some addresses but
> not all, espicialy the base address (status register) (ISEQ has no clue)

Are you sure it's always the next address, or just on addresses that have
a particular address line low (or high)?  This sounds like one of the
address lines is floating high, which would explain why some registers
read OK (where that address line is driven high anyway) and some don't
(where the line needs to be low).

This is an indication that the module doesn't meet the VME spec, which
does allow for address pipelining.  PowerPC CPU modules using the Universe
chip generate rather different signal timings to the older 68K-based
interfaces, and some boards aren't properly designed to the spec, just to
what the manufacturer thinks the signals do.

- Andrew
-- 
Larry McVoy: "Learn how to think in C++ but don't ever program in it."

References:
Re: ISEG VHQ204L Driver ahed aladwan

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