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<== Date ==> <== Thread ==>

Subject: Re: ISEG VHQ204L Driver
From: ahed aladwan <ahed.aladwan@psi.ch>
To: "Leng, Yongbin" <leng@bnl.gov>, tech-talk <tech-talk@aps.anl.gov>
Date: Wed, 24 Jul 2002 15:58:10 +0200
Hi All,

I got the driver from kristi luchini in SLAC, ftp.slac.stanford.edu

But I have another preoblems with the ISEQ VHQ202 VME module:

When the master (PPC MVME2304, vxWork 5.3.1) reads the data from the slave (A16, D16, address mod is 0x2D or 0x29), it seems that for some addresses the master get the data for the next address (+ 1 byte), using a logic analyzer to check the master read cycle (attached pdf file), I have noticed that because the master apply address pipelining (forcasting) and the slave dosen't latch the data (or address), I got wrong data.
But what I can't understand why this happens only for some addresses but not all, espicialy the base address (status register) (ISEQ has no clue)
Is it a bad design of the slave or there is something unclear for me in the master configuration, what is the situation with other labs who uses similar card model and different IOC, moreover according to Tundra (universe chip, PCI - VME bridge) it is not possible to disable address pipelining.


I appreciate any suggestions.

Best regards,
Ahed Aladwan


Leng, Yongbin wrote:


Hi Guys,

SNS diagnostic controls is planing to use ISEG VHQ204L in BLM system.
And someone told me its EPICS driver is available. But I can't find it on
EPICS homepage.
Does anyone have EPICS driver for VHQ204L and can shared it with us?

Thanks in advance.

Yongbin Leng
631-344-2835
SNS controls, BNL
UPTON, NY 11973



-- ==== Ahed AlAdwan, WSLA/208, Swiss Light Source / Paul Scherrer Institut, CH-5232 Villigen ==== phone: +41-56-3104594 fax: +41-56-3104413 ==== mailto:ahed.aladwan@psi.ch http://www.psi.ch


Attachment: vhq_read_cycle.pdf
Description: Adobe PDF document

Attachment: Read cycle_IEC821.pdf
Description: Adobe PDF document


Replies:
Re: ISEG VHQ204L Driver Andrew Johnson
RE: ISEG VHQ204L Driver Jeff Hill

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