Experimental Physics and
Industrial Control System

[email protected] (Bob Dalesio) · Fri, 27 May 94 09:05:01 MDT

  There are several problems in the current addressing scheme that certainly
  need to be handled. The one that we have been dealing with the longest 
  concerns having too little information to pass between the database and the
  device drivers to effectively configure and address them. As stated before,
  this causing the driver writer considerable pain when adding a new I/O bus,
  such as CAMAC or Bitbus. 

  The reflective memory problem is more akin to the name space situation in
  EPICS. Names are defined in many different databases, however, they must be
  unique on the network. We currently report when more than one IOC responds
  to a channel name request. (Does this go to logMsg so that it's available
  to anyone analyzing the system performance?)

  As we move to an ASCII database format that is loaded at IOC initialization, 
  more and more consistency checking is done at initialization. It may be that 
  this reflective memory scheme could be checked then.

  A little excursion into a strawperson design: 
  Develop a reflective memory resource manager or set or routines that
  allocates blocks of memory as named, logical address space. The addressing
  in the database then become a logical name address pair (much like the
  current address space). The first access to each address space would then
  need to specify if it was the master (owned the logical name) or the slave
  (used the contents of the logical space). The first reference to the name
  device would allocate a fixed size logical device block (simplify the
  initial implementation and address checking - it would be easier to do variable
  sized if we had a better interface to the device layer). If it was the master, 
  then the reference would be successful. If it was the slave that first made thereference, then the device support would return failure and mark the record
  as INVALID. This would allow control loops to "open" if the needed parameters
  were not available. This handles the initialization of IOC's occuring at
  different times. (What is the power up state of a reflective memory? The state
  of all of the other memory that it is reflecting or does it propagate some
  values into the other memories?) The conversion of logical name to physical
  address would be in the reflective memory (hopefully this saves it when
  any machine is up). Each logical address space should also have a heartbeat
  to indicate that the master IOC, device driver, etc.. are still healthy.
  The device support should also have a reboot hook that marks the logical
  space over which it has control, as rebooting. As a first pass, logical
  name space has these states; not defined, no master initialization, rebooting,
  no heart-beat (dead - at least sick), healthy. If more than one IOC claims to
  be master of a logical name space, this generates a logMsg alarm into the
  system error logger.

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Experimental Physics and Industrial Control System

Experimental Physics and
Industrial Control System