Table of Contents


CHAPTER 1 CHAPTER 1 VME System Monitor Board

1.1 System Monitor Introduction

Much of the machinery throughout the APS will be controlled by VME based computers. In order to increase the reliability of the system, it is necessary to be able to monitor the status of each VME crate. In order to do this, a VME System Monitor was created. In addition to being able to monitor and report the status (watchdog timer, temperature, CPU (Motorola MVME 167) state (status, run, fail), and the power supply), it includes provisions to remotely reset the CPU and VME crate, digital I/O, and parts of the transition module (serial port and ethernet connector) so that the Motorla MVME 712 is not needed. The standard VME interface was modified on the System Monitor so that in conjunction with the Motorola MVME 167 a message based VXI interrupt handler could is implemented.

The System Monitor is a single VME card (6U). It utilizes both the front panel and the P2 connector for I/O. The front panel contains a temperature monitor, watchdog status LED, 4 general status LEDs, input for a TTL interrupt, 8 binary inputs (24 volt, 5 volt, and dry contact sense), 4 binary outputs (dry contact, TTL, and 100 mA), serial port (electrical RS-232 or fiber optic), ethernet transceiver (10 BASE-FO or AUI), and a status link to neighbor crates. The P2 connector is used to provide the serial port and ethernet to the processor. In order to abort and read the status of the CPU, a jumper cable must be connected between the CPU and the System Monitor.

1.2 System Monitor Theory of Operation

The System Monitor consists of basically four sections; a VME interface which allows the reading and writing of the board functions, a status link which connects to neighboring crates using a serial fiber optic link, a serial port which allows for a CPU abort and a VME reset, and the physical connections for the console serial port and the ethernet.

1.2.1 VME Interface

The VME interface on the System Monitor was created by Bob Laird (1993). Added to this interface is the ability to capture 16 bit interrupt vectors. The MVME 167 is only able to latch the lower 8 bits of an interrupt vector, so this card expands the capabilities of the processor. When an interrupt is generated, the System Monitor will capture the presented 16 bit interrupt vector. This vector can then be recovered from the System Monitor board by reading functions 25 - 31, which correspond to IRQ1 - IRQ7 respectively.

The interrupt vector which the System Monitor can generate from any one of its binary inputs, is stored at the function 23 memory location.

In order to make the MVME 167 compatible with VXI message based interrupts, it was necessary to create a module which sits at memory location 0xC008. This module contains, in essence, a full VME interface. When the memory location 0xC008 is written to, the message is captured, and an interrupt is generated. This vector is controlled by function 24. The MVME 167 can then read back the message word, which is stored at location 0xC008.

The System Monitor essentially sits at two memory locations on the VME bus. The VME interface is configured to any valid memory location, but the VXI message based interrupter is hardwired to sit at 0xC000, function 4 (0xC008).

If the VXI message based interrupts are not going to be used, then it is not necessary to include some of the circuitry on the System Monitor. VME PLD B (U41), VME INTERRUPTER B (U42), and CONTROL REGISTER AND INT VECTOR (U43) are not necessary. If these PLDs are taken out, then it is necessary to insert JP26, JP27, JP28, and JP29, J8 and J9 should be removed. This will bypass all of the critical signals which these ICs would normally supply.

1.3 Status Link / Character Detector

The status link is used to both transmit basic status information to a neighboring VME crate and to receive this information from a neighboring crate. This status includes the state of the watchdog timer, temperature, CPU status, CPU run status, voltage (both +12V/-12V and +5V), and the CPU fail status. The physical link is implemented with fiber optics based upon the serial port standard (9600, 1 start bit, 7 data bits, no parity). The status information is located at function 18. The received status is the lower order byte, and the status to be sent out can be monitored on the higher order byte.

The character detector monitors the console serial port for a specific sequence of characters. A Control-X should normally reset the VxWorks Software. Occasionally the CPU will "hang" and without this character detector, it would be necessary to physically go out to the crate and manually reset it. With the System Monitor Board, sending a Control-X followed immediately by a Control-Y will abort the CPU. If this still does not clear up the problem, a Control-X followed by a Control-Y and a Control-Z (this sequence must be completed in 500 mS) will reset the VME backplane.

A jumper cable (J5) must be installed between the MVME 167 and the System Monitor in order to take advantage of the remote monitoring of the CPU statuses and the CPU abort signal.

1.4 Digital I/O

The System Monitor has four digital outputs and 8 digital inputs (P3). The outputs are current limiting solid state relays (120 mA) and can be either TTL, dry contact, or 100 mA. This is determined by the configuration jumpers (JP1 - JP4, JP21-24). The binary inputs can be configured for 12V-28V inputs, 5V-10V inputs, and dry contact sense using jumpers JP5 - JP20. The binary outputs are located in the lower order nibble of function 19. The binary inputs are located in the high order byte of function 19.

In addition the binary inputs can also be used to interrupt the VME backplane. These interrupts are maskable, and the mask is the low order byte of function 20.

Located on the front panel is a TTL input which is also a maskable interrupt. The mask for this bit is the least significant bit of the high order byte of function 20.

JP?? determines if the fourth digital output echoes that status of the OUT3 bit or the status of the watchdog timer. Echoing the status of the watchdog timer allows an external system, such as an Allen-Bradley Binary Input Module to monitor the watchdog status of the CPU.

1.5 Temperature Monitor

The sensor used is a three pin (TO-92 package) device (U2) which can be mounted anywhere in the crate. There is a place on top of the board for this sensor so that it can measure the temperature of the air after it has been blown over the crate. This temperature is then displayed on the front panel using LEDs. The temperature can also be read back in the lower order byte of function 21. JP25 is used to configure the TEMP_OK level which is passed on to the status link. The range which can be measured is from 20 τo 65 ιν 5 στεσ.

1.6 Voltage Monitor / Watchdog Timer

Both the +12 Volt and the -12 Volt supply are monitored for under voltage. The +5 Volt supply is monitored for both over and under voltage. The statuses are fed to the Status Link. The +12 Volt and -12 Volt can fall by about 10% before the comparator trips, and the +5 Volt supply is monitored to about +0.1 Volt and - 0.4 Volt.

The watchdog is triggered by a read function to the board. The board must be read from every 1.6 seconds or the watchdog will time out. This status is echoed to the Status Monitor as well as the front panel. There is a bi-colored LED on the front panel, green indicates that the CPU is polling the System Monitor, and red indicates that the CPU has stopped.

In addition to a watchdog timer, this function also contains a latch, whose status is echoed by four front panel LEDs (yellow). The LEDs echo the bits in the lower order nibble of function 22. One possible use for these LEDs is to indicate the boot status of the CPU.

1.7 Serial Port

Rather than use the MVME 712 transition module to break out the console serial port, it was decided that it would be put on the front panel of the System Monitor. It is designed to be a daughter board so that it could either implement electrical RS-232 or a standard fiber optic protocol. The advantage of this scheme is that the fiber optic serial port will be used throughout the APS because of its immunity to electrical noise and at least 1 KM distance limitation, while standard RS-232 will be used for test and development in the laboratory setting.

It is assumed that the console port will be set to the default configuration of 9600 baud, 1 start bit, 8 data bits, and no parity (9600,1,8,N). This default configuration is hard wired into the part of the circuit which monitors the serial port in order to detect a reset sequence.

1.8 Ethernet Port

Like the serial port, to avoid the need for the transition module, an ethernet connector would be included on the front panel. It was decided that initially only an AUI connector would be offered on a daughter board. This would allow the board to stay compatible with future ethernet implementations.

1.9 P2

The P2 connector is used to connect the console and ethernet ports on the System Monitor to the MVME 167. Since only rows A and C are necessary for this, a simple 64 pin mass terminated jumper cable can be used.

1.10 Function Map of the System Monitor

The System Monitor utilizes functions 18 - 31. These functions were chosen so that future integration of the System Monitor with the APS Event Receiver would be easier to implement.

TABLE 1. FUNCTION DESCRIPTION 
--------------------------------------------------------------------------------------------------------
Function #  Function Name      Name                             Description                               
--------------------------------------------------------------------------------------------------------
18 (LSB)    Status Link RX     rWATCHDOG_OK (lsb)               Watchdog status - bit 0                   
                               rnTEMP_OK                        Temperature status - bit 1                
                               rnSTAT                           CPU status - bit 2                        
                               rnRUN                            CPU running status - bit 3                
                               r5_OK                            5 Volts OK - bit 4                        
                               r+-12_OK                         +-12 &sfgr;oλτσ OK - ιτ 5                     
                               rnFAIL                           CPU failure - bit 6                       
                               START_BIT                        Undefined - bit 7                         
18 (MSB)    Status Link TX     WATCHDOG_OK                      Watchdog status - bit 8                   
                               nTEMP_OK                         Temperature status - bit 9                
                               nSTAT                            CPU status - bit 10                       
                               nRUN                             CPU running status - bit 11               
                               5_OK                             5 Volts OK - bit 12                       
                               +-12_OK                          +-12 Volts OK - bit 13                    
                               nFAIL                            CPU failure - bit 14                      
                               START_BIT (msb)                  Undefined - bit 15                        
19 (LSB)    Digital Output     OUTPUT[0..3]                     Dry Contact, TTL, 100mA                   
                               (reserved bits[4..7])                                                      
19 (MSB)    Digital Input      INPUT[0..7]                      Dry Contact, 5V-28V                       
20          Interrupt Mask     INPUT[0..6], TTL INPUT,          Inputs to generate a VME interrupt        
                               (reserved bits[8..15]                                                      
21          Temp Monitor       20 C - 65 C bits[0..7],          This is a bar graph where each bit repre  
                               (reserved bits[8..15]            sents 5 C.                                
22          Watchdog           LED[0..3], Automatic_Reset[7],   Front panel LEDs to show boot status,     
                               (reserved bits[4..6, 8..15]      and enable bit for automatic reboot on    
                                                                watchdog time-out.                        
23          0xC008 Int Vector  DB[0..15]                        Vector presented when location 0xC008     
                                                                is written to, (capture of VXI)           
24          VME Int Vector     DB[0..15]                        VME interrupt vector, user defined        
25          IRQ 1 Vector       DB[0..15]                        Captured 16 bit VXI IRQ1 Vector           
26          IRQ 2 Vector       DB[0..15]                        Captured 16 bit VXI IRQ1 Vector           
27          IRQ 3 Vector       DB[0..15]                        Captured 16 bit VXI IRQ1 Vector           
28          IRQ 4 Vector       DB[0..15]                        Captured 16 bit VXI IRQ1 Vector           
29          IRQ 5 Vector       DB[0..15]                        Captured 16 bit VXI IRQ1 Vector           
30          IRQ 6 Vector       DB[0..15]                        Captured 16 bit VXI IRQ1 Vector           
31          IRQ 7 Vector       DB[0..15]                        Captured 16 bit VXI IRQ1 Vector           
                                                                                                          
--------------------------------------------------------------------------------------------------------

1.11 Configuration

1.11.1 JP1 - JP4, JP21 - JP24 : Digital Output

JP1, JP3, JP21, and JP23 are installed when the output is to be TTL or 100 mA.
JP2, JP4, JP22, and JP24 are installed when the output is to be TTL.
No jumpers are inserted for a Dry Contact output.

A Dry Contact output is connected between OUT+ and OUT-.
A TTL or 100 mA output is connected between OUT- and GROUND.

TABLE 2. Digital Output Configuration 
------------------------------------------------------------------
JP[1, 3, 21, 23]  JP[2, 4, 22, 24]  CONFIGURATION                   
------------------------------------------------------------------
IN                IN                TTL (OUT-, GROUND)              
IN                OUT               100 mA (OUT-, GROUND)           
OUT               OUT               Dry Contact Sense (OUT+, OUT-)  
                                                                    
------------------------------------------------------------------

1.11.2 JP5 - JP20 : Digital Input

All of the jumpers are removed for a 12V - 28V input, between IN+ and IN-.
JP5, JP7, JP9 ... JP19 (JP A) are inserted for a 5V - 10V input, between IN+ and IN-.
JP6, JP8, JP10 ... JP20 (JP B) are inserted for a Dry Contact Sense input, between IN- and GROUND.

TABLE 3. Digital Input Configuration 
-------------------------------------------
JP A  JP B  CONFIGURATION                    
-------------------------------------------
OUT   OUT   12V - 28V input (IN+, IN-)       
IN    OUT   5V - 10V input (IN+, IN-)        
OUT   IN    Dry Contact Sense (IN-, GROUND)  
                                             
-------------------------------------------

1.11.3 J6 - J9 : Interrupt Level

These jumpers determine which interrupt request level is used by the corresponding VME module. JP6 and JP7 are for the System Monitor IRQ level. JP8 and JP9 determine which level the VXI message based interrupt generates.

TABLE 4. Jumpers J6 and J8 
----------------------------------------------------------
Pins 1-2  Pins 3-4  ...  Pins 11-12  Pins 13-14  INT Level  
----------------------------------------------------------
OUT       OUT       OUT  OUT         OUT         DISABLED   
IN        OUT       OUT  OUT         OUT         1          
OUT       IN        OUT  OUT         OUT         2          
OUT       OUT       ...  OUT         OU          [3..5]     
OUT       OUT       OUT  IN          OUT         6          
OUT       OUT       OUT  OUT         IN          7          
                                                            
----------------------------------------------------------
TABLE 5. Jumpers J7 and J9 
---------------------------------------
Pins 1-2  Pins 3-4  Pins 5-6  INT Level  
---------------------------------------
OUT       OUT       OUT       DISABLED   
IN        OUT       OUT       1          
IN        IN        OUT       2          
...       ...       ...       ...        
OUT       IN        IN        6          
IN        IN        IN        7          
                                         
---------------------------------------

1.11.4 JP25 : Temperature Monitor

This determines the set point at which the nTEMP_OK signal is set. This level can range from 20 (ινσ 19-20) τo 65 (ινσ 1-2) ιν 5 ινχρεεντσ.

1.11.5 JP26 - JP29 : VXI Message Based Interrupt

When these jumpers are installed, the VXI Message based interrupt handler will be disabled on the System Monitor. These jumpers should also be installed if the VME_PLD_B (U41), VME_INTERRUPTER_B (U42), and INT (U43) are not present on the board.

FIGURE 1 Configuration Jumper Placement on the System Monitor Board

1.12 System Monitor Assembly

The System Monitor is a standard VME (6U) card. If the status of the processor is to be monitored by the card, it is necessary that the card be placed in the slot adjacent to the processor. There is a short ribbon cable which attaches the two card. Due to the placement of the connector on the MVME-167, it was necessary to place the corresponding connector on the System monitor board in the same position, by the front panel. The ribbon cable is to be run between the circuit board and the front panel. Once the cable is in place, it will be necessary to take out both boards together if either one needs to be serviced.

The Ethernet and serial connection between the System Monitor and the processor utilize the P2 connector on the VME backplane. The A and C rows of each board's P2 connector must be connected together. This can be done using mass terminated 64 pin ribbon cable. This cable is then installed on the rear of the VME crate.

The completed System Monitor Board will contain three daughter boards. One is for the Ethernet connection. In the first version this will just be an AUI connector, the signals from the AUI connector are essentially jumperred from the front panel of the System Monitor to the P2 of the MVME-167.

Another daughter board is for the console serial port. This daughter board will either be an electrical or fiber optic RS-232 transceiver. The two options are offered so that in the laboratory setting the standard (and convenient) electrical interface can be used, and when the boards are installed in the Advanced Photon Source the noise immune fiber optic interface can be used. The transceiver converts the incoming serial signal to TTL levels so that it can be monitored for the reset sequence and then back to RS-232A levels for use by the processor.

The third daughter board is used for the status link between the boards. The circuitry on this board is identical to that on fiber optic transceiver board, except that the MAX233 chip is omitted and pins 19 and 20 are jumperred. This third daughter board was created to make room for cable which supplies the status information from the CPU to the System Monitor.

1.13 Device Support

The System Monitor Board supports Binary Output (BO), Binary Inputs (BI), MultiBit Binary Output (MBBO), and MultiBit Binary Input (MBBI). When defining a Process Variable, one should choose the "SYSMON" device option. The card number indicates which System Monitor Board you are accessing in a particular crate (typically this field will be equal to 0). The signal field acts as a mask so that you can specify which bit you are accessing with a BO or a BI. The Parameter field then contains the name of the register you want to access:

TABLE 6. Device Support Parameter Field Entry Options 
----------------------------------------------------
Parameter    Corresponding Register                   
----------------------------------------------------
StatusLink   Status Link                              
Dio          Digital I/O                              
IntMask      Interrupt Mask                           
Temperature  Temperature Monitor                      
Watchdog     Watchdog LEDs / Enable Reset             
VXIVector    0xC008 Interrupt Vector                  
IntVector    VME Interrupt Vector for System Monitor  
IRQ1         Captured IRQ 1 Vector                    
IRQ2         Captured IRQ 2 Vector                    
IRQ3         Captured IRQ 3 Vector                    
IRQ4         Captured IRQ 4 Vector                    
IRQ5         Captured IRQ 5 Vector                    
IRQ6         Captured IRQ 6 Vector                    
IRQ7         Captured IRQ 7 Vector                    
----------------------------------------------------
The Process Variable indicating the Temperature Monitor is meant to be a MBBI. In the device support for the System Monitor Board (devSysmon.c), upon initialization, the record for the MBBI variable is configured to report the proper temperature in Celsius if the Temperature parameter is specified. The bit pattern fields (ZRVL .. FFVL), string fields (ZRST .. FFST) and the number of bits field (NOBT) are preloaded with the proper values.