MVME162 Board Setup
This file should help you set up your mvme162 board to run the stand alone
HiDEOS. This is meant to help with the first mvme162 added to the crate.
What You Are Doing
Here is what you are actually doing by performing the actions listed in this
file.
- Setting up your 162 to boot from Motorola's 162bug debug monitor.
The 162 will be set up NOT to be system controller.
- The adjustments to the environment parameters will determine where the
162 memory will appear to the processor and to the VMEbus. The
parameters also define important interprocessor communication
information.
- The first 162 board (in addition to the main IOC processor) will
appear on the VMEbus at 0x80000000 through 0x80000000+size of your
boards memory. (programming the Slave address decoder)
- The first 162 board will be able to access memory from the VMEbus
from 0x00000000 through 0x7fffffff. This is the memory mapped to
vxWorks. (programming the Master address decoder)
- The DRAM controller will be set up so local memory appears from
address 0x80000000 to 0x80000000+size of your 162 memory.
- Each processor in the crate with a VMEchip2 will advertise itself
in a small global block of memory in D16/A16 space. For our system
this block begins at 0x0000. Setting the GCSR group address
defines this to the system. The vxWorks IOC system controller
is assigned as board 0 and gets the first entry at 0x0000. Each
additional processor is assigned a value from 1 to 15, which in
an index into this global block. Each processor gets about 16 bytes.
The first 162 is assigned a board address of 1, so it gets the
second entry in the group table. All processors can probe the group
block to find out what other processors are available on the
VMEbus. This system uses mailbox interrupts; this block
contains the mailboxes and interprocessor communication points.
Set the jumpers on the mvme162
- J1 - 1 out
- J20 - (1-2) (2-3)
- J21 - (2-3)
- J22 - (9-10) out, (15-16) out, all others in
162Bug
Your board should have come with a 162bug ROM or it should have the 162bug
monitor from motorola in flash memory. This version of HiDEOS uses the
162bug to start the board. Hook up a serial cable and terminal to the
console port and procede.
162Bug Environment Parameters
Set the 162bug environment parameters. At the 162bug prompt, type env
to adjust the environment parameters.
Leave everything as is except the following:
- Base Address of Dynamic Memory = 80000000?
- Slave Enable #1 [Y/N] = Y?
- Slave Starting Address #1 = 80000000?
- Slave Ending Address #1 = 800FFFFF? <-----starting address + size of memory
- Slave Address Translation Address #1 = 80000000?
- Slave Address Translation Select #1 = FFF00000? <----FFF0=1MB
NOTE: for above, FFF0=1MB,FFC0=4MB,FF80=8MB,FF00=16MB
- Slave Control #1 = 03EF?
- Slave Enable #2 [Y/N] = N?
- Slave Starting Address #2 = 00000000?
- Slave Ending Address #2 = 00000000?
- Slave Address Translation Address #2 = 00000000?
- Slave Address Translation Select #2 = 00000000?
- Slave Control #2 = 0000?
- Master Enable #1 [Y/N] = Y?
- Master Starting Address #1 = 00000000?
- Master Ending Address #1 = 7FFFFFFF?
- Master Control #1 = 0D?
- Master Enable #2 [Y/N] = N?
- Master Starting Address #2 = 00000000?
- Master Ending Address #2 = 00000000?
- Master Control #2 = 00?
- Master Enable #3 [Y/N] = N?
- Master Starting Address #3 = 00100000?
- Master Ending Address #3 = 00FFFFFF?
- Master Control #3 = 3D?
- Master Enable #4 [Y/N] = N?
- Master Starting Address #4 = 00000000?
- Master Ending Address #4 = 00000000?
- Master Address Translation Address #4 = 00000000?
- Master Address Translation Select #4 = 00000000?
- Master Control #4 = 00?
- Short I/O (VMEbus A16) Enable [Y/N] = Y?
- Short I/O (VMEbus A16) Control = 01?
- F-Page (VMEbus A24) Enable [Y/N] = Y?
- F-Page (VMEbus A24) Control = 02?
- VMEC2 GCSR Group Base Address = 00?
- VMEC2 GCSR Board Base Address = 01?
Be sure not to rush through the parameters at the end, the monitor will
prompt for an update confirmation at the end of the parameter list.
The default is "no" for the update confirmation.
Argonne National Laboratory
Copyright
Information
Jim Kowalkowski ([email protected]) updated 4/12/95