Version 1.20 (January 2005)
Hardware Register Map
|
Register |
Name |
|---|---|
|
0 |
Control / Status |
|
1 |
RAM Address |
|
2 |
RAM Data |
|
3 |
Fine Delay |
|
4 |
P0/Course Delay |
Hardware
Register to PV Mapping
|
Register |
L. Bit |
N. Bits |
Contents |
Rec. Type |
Process Variable Name |
|---|---|---|---|---|---|
|
0 |
0 |
1 |
Running |
BI |
S$(UNITBnchClkGenRunningBI |
|
1 |
1 |
P0 Detect |
BI |
S$(UNIT)BnchClkGenP0DetectBI |
|
|
2 |
1 |
Disable |
BI |
S$(UNIT)BnchClkGenDisableBI |
|
|
2 |
1 |
Disable |
BO |
S$(UNIT)BnchClkGenDisableBO |
|
|
3 |
0 |
16 |
Fine Delay |
AI |
S$(UNIT)BnchClkGenFineDelayAI |
|
0 |
16 |
Fine Delay |
AO |
S$(UNIT)BnchClkGenFineDelayAO |
|
|
4 |
0 |
16 |
P0 Delay |
AI |
S$(UNIT)BnchClkGenP0DelayAI |
|
0 |
16 |
P0 Delay |
AO |
S$(UNIT)BnchClkGenP0DelayAO |
Software
Register to PV Mapping
|
Register |
L. Bit |
N. Bits |
Contents |
Rec. Type |
Process Variable Name |
|---|---|---|---|---|---|
|
0 |
0 |
16 |
Bucket Number |
AO |
S$(UNIT)BnchClkGenSetBucketAO |
|
0 |
16 |
Bucket List |
WAVEFORM |
S$(UNIT)BnchClkGenBucketsWF |
|
|
1 |
0 |
16 |
Bucket Number |
AO |
S$(UNIT)BnchClkGenReSetBuckAO |
|
0 |
16 |
Pattern |
WAVEFORM |
S$(UNIT)BnchClkGenPatternWF |
|
|
0 |
16 |
Clear RAM |
BO |
S$(UNIT)BnchClkGenClearPatBO |
|
|
2 |
0 |
16 |
Write RAM |
BO |
S$(UNIT)BnchClkGenWritePatBO |
Additional
PVs
|
Process Variable Name |
|---|
|
S$(UNIT)BnchClkGenLoadPatBO |
|
S$(UNIT)BnchClkGenAutoLoadBO |
|
S$(UNIT)BnchClkGenClearMessB |
|
S$(UNIT)BnchClkGenMessageSI |
|
S$(UNIT)BnchClkGenListWF |